mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-17 17:24:17 +08:00
63a4b52c9d
Patch from Ian Campbell The sparse warning initially surfaced in sound/arm/pxa2xx-ac97.c because it was using u32 * variables to hold the unsigned long * register addresses. I submitted an ALSA patch for this http://thread.gmane.org/gmane.linux.alsa.devel/27804 issue and it was suggested that it might be preferable to change the register definitions to use u32. Most other subarches seem to use u32 for their register type, at least the ones which use a __REG macro (like the PXA) do. Nico indicated in the thread above that he wouldn't mind this patch. Changing the type required fixes for opposite warnings in the pxa2xx usb gadget code but that was the only new warning introduced on defconfig or lubbock, mainstone and our own PXA255 boards. Signed-off-by: Ian Campbell <icampbell@arcom.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
84 lines
2.2 KiB
C
84 lines
2.2 KiB
C
/*
|
|
* linux/include/asm-arm/arch-pxa/hardware.h
|
|
*
|
|
* Author: Nicolas Pitre
|
|
* Created: Jun 15, 2001
|
|
* Copyright: MontaVista Software Inc.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
#ifndef __ASM_ARCH_HARDWARE_H
|
|
#define __ASM_ARCH_HARDWARE_H
|
|
|
|
/*
|
|
* We requires absolute addresses.
|
|
*/
|
|
#define PCIO_BASE 0
|
|
|
|
/*
|
|
* Workarounds for at least 2 errata so far require this.
|
|
* The mapping is set in mach-pxa/generic.c.
|
|
*/
|
|
#define UNCACHED_PHYS_0 0xff000000
|
|
#define UNCACHED_ADDR UNCACHED_PHYS_0
|
|
|
|
/*
|
|
* Intel PXA2xx internal register mapping:
|
|
*
|
|
* 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
|
|
* 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
|
|
* 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
|
|
* 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
|
|
* 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
|
|
* 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
|
|
* 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
|
|
*
|
|
* Note that not all PXA2xx chips implement all those addresses, and the
|
|
* kernel only maps the minimum needed range of this mapping.
|
|
*/
|
|
#define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
|
|
#define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
# define __REG(x) (*((volatile u32 *)io_p2v(x)))
|
|
|
|
/* With indexed regs we don't want to feed the index through io_p2v()
|
|
especially if it is a variable, otherwise horrible code will result. */
|
|
# define __REG2(x,y) \
|
|
(*(volatile u32 *)((u32)&__REG(x) + (y)))
|
|
|
|
# define __PREG(x) (io_v2p((u32)&(x)))
|
|
|
|
#else
|
|
|
|
# define __REG(x) io_p2v(x)
|
|
# define __PREG(x) io_v2p(x)
|
|
|
|
#endif
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
/*
|
|
* Handy routine to set GPIO alternate functions
|
|
*/
|
|
extern void pxa_gpio_mode( int gpio_mode );
|
|
|
|
/*
|
|
* Routine to enable or disable CKEN
|
|
*/
|
|
extern void pxa_set_cken(int clock, int enable);
|
|
|
|
/*
|
|
* return current memory and LCD clock frequency in units of 10kHz
|
|
*/
|
|
extern unsigned int get_memclk_frequency_10khz(void);
|
|
extern unsigned int get_lcdclk_frequency_10khz(void);
|
|
|
|
#endif
|
|
|
|
#endif /* _ASM_ARCH_HARDWARE_H */
|