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Tegra124 has 4 MMC controllers just like previous versions of the SoC. Note that there are some non-backwards-compatible HW differences, and hence a new DT compatible value must be used to describe the HW. Also enable the relevant controllers in the Venice2 board DT. power-gpios property suggested by Thierry Reding. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com>
53 lines
974 B
Plaintext
53 lines
974 B
Plaintext
/dts-v1/;
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#include "tegra124.dtsi"
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/ {
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model = "NVIDIA Tegra124 Venice2";
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compatible = "nvidia,venice2", "nvidia,tegra124";
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memory {
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reg = <0x80000000 0x80000000>;
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};
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serial@70006000 {
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status = "okay";
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};
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pmc@7000e400 {
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nvidia,invert-interrupt;
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nvidia,suspend-mode = <1>;
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nvidia,cpu-pwr-good-time = <500>;
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nvidia,cpu-pwr-off-time = <300>;
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nvidia,core-pwr-good-time = <641 3845>;
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nvidia,core-pwr-off-time = <61036>;
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nvidia,core-power-req-active-high;
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nvidia,sys-clock-req-active-high;
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};
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sdhci@700b0400 {
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cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
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power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
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status = "okay";
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bus-width = <4>;
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};
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sdhci@700b0600 {
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status = "okay";
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bus-width = <8>;
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};
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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clk32k_in: clock@0 {
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compatible = "fixed-clock";
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reg=<0>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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};
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