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a094c2fa09
The driver has been successfully tested with Xilinx's core axi-quad-spi-1.0.0a. Documented on DS843: https://www.xilinx.com/support/documentation/ip_documentation/axi_quad_spi/v1_00_a/ds843_axi_quad_spi.pdf Cc: Mark Brown <broonie@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
542 lines
14 KiB
C
542 lines
14 KiB
C
/*
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* Xilinx SPI controller driver (master mode only)
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*
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* Author: MontaVista Software, Inc.
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* source@mvista.com
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*
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* Copyright (c) 2010 Secret Lab Technologies, Ltd.
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* Copyright (c) 2009 Intel Corporation
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* 2002-2007 (c) MontaVista Software, Inc.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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#include <linux/spi/xilinx_spi.h>
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#include <linux/io.h>
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#define XILINX_SPI_MAX_CS 32
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#define XILINX_SPI_NAME "xilinx_spi"
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/* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
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* Product Specification", DS464
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*/
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#define XSPI_CR_OFFSET 0x60 /* Control Register */
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#define XSPI_CR_LOOP 0x01
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#define XSPI_CR_ENABLE 0x02
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#define XSPI_CR_MASTER_MODE 0x04
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#define XSPI_CR_CPOL 0x08
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#define XSPI_CR_CPHA 0x10
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#define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL | \
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XSPI_CR_LSB_FIRST | XSPI_CR_LOOP)
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#define XSPI_CR_TXFIFO_RESET 0x20
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#define XSPI_CR_RXFIFO_RESET 0x40
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#define XSPI_CR_MANUAL_SSELECT 0x80
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#define XSPI_CR_TRANS_INHIBIT 0x100
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#define XSPI_CR_LSB_FIRST 0x200
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#define XSPI_SR_OFFSET 0x64 /* Status Register */
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#define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */
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#define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */
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#define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */
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#define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */
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#define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */
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#define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */
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#define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */
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#define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
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/* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
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* IPIF registers are 32 bit
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*/
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#define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */
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#define XIPIF_V123B_GINTR_ENABLE 0x80000000
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#define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */
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#define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */
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#define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */
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#define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while
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* disabled */
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#define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */
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#define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */
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#define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */
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#define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */
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#define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */
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#define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */
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#define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */
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struct xilinx_spi {
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/* bitbang has to be first */
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struct spi_bitbang bitbang;
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struct completion done;
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void __iomem *regs; /* virt. address of the control registers */
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int irq;
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u8 *rx_ptr; /* pointer in the Tx buffer */
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const u8 *tx_ptr; /* pointer in the Rx buffer */
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u8 bytes_per_word;
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int buffer_size; /* buffer size in words */
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u32 cs_inactive; /* Level of the CS pins when inactive*/
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unsigned int (*read_fn)(void __iomem *);
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void (*write_fn)(u32, void __iomem *);
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};
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static void xspi_write32(u32 val, void __iomem *addr)
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{
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iowrite32(val, addr);
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}
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static unsigned int xspi_read32(void __iomem *addr)
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{
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return ioread32(addr);
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}
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static void xspi_write32_be(u32 val, void __iomem *addr)
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{
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iowrite32be(val, addr);
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}
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static unsigned int xspi_read32_be(void __iomem *addr)
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{
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return ioread32be(addr);
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}
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static void xilinx_spi_tx(struct xilinx_spi *xspi)
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{
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u32 data = 0;
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if (!xspi->tx_ptr) {
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xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
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return;
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}
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switch (xspi->bytes_per_word) {
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case 1:
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data = *(u8 *)(xspi->tx_ptr);
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break;
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case 2:
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data = *(u16 *)(xspi->tx_ptr);
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break;
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case 4:
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data = *(u32 *)(xspi->tx_ptr);
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break;
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}
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xspi->write_fn(data, xspi->regs + XSPI_TXD_OFFSET);
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xspi->tx_ptr += xspi->bytes_per_word;
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}
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static void xilinx_spi_rx(struct xilinx_spi *xspi)
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{
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u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
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if (!xspi->rx_ptr)
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return;
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switch (xspi->bytes_per_word) {
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case 1:
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*(u8 *)(xspi->rx_ptr) = data;
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break;
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case 2:
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*(u16 *)(xspi->rx_ptr) = data;
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break;
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case 4:
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*(u32 *)(xspi->rx_ptr) = data;
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break;
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}
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xspi->rx_ptr += xspi->bytes_per_word;
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}
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static void xspi_init_hw(struct xilinx_spi *xspi)
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{
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void __iomem *regs_base = xspi->regs;
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/* Reset the SPI device */
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xspi->write_fn(XIPIF_V123B_RESET_MASK,
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regs_base + XIPIF_V123B_RESETR_OFFSET);
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/* Enable the transmit empty interrupt, which we use to determine
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* progress on the transmission.
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*/
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xspi->write_fn(XSPI_INTR_TX_EMPTY,
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regs_base + XIPIF_V123B_IIER_OFFSET);
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/* Disable the global IPIF interrupt */
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xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
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/* Deselect the slave on the SPI bus */
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xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
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/* Disable the transmitter, enable Manual Slave Select Assertion,
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* put SPI controller into master mode, and enable it */
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xspi->write_fn(XSPI_CR_MANUAL_SSELECT | XSPI_CR_MASTER_MODE |
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XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET | XSPI_CR_RXFIFO_RESET,
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regs_base + XSPI_CR_OFFSET);
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}
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static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
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{
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struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
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u16 cr;
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u32 cs;
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if (is_on == BITBANG_CS_INACTIVE) {
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/* Deselect the slave on the SPI bus */
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xspi->write_fn(xspi->cs_inactive, xspi->regs + XSPI_SSR_OFFSET);
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return;
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}
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/* Set the SPI clock phase and polarity */
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cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_MODE_MASK;
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if (spi->mode & SPI_CPHA)
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cr |= XSPI_CR_CPHA;
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if (spi->mode & SPI_CPOL)
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cr |= XSPI_CR_CPOL;
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if (spi->mode & SPI_LSB_FIRST)
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cr |= XSPI_CR_LSB_FIRST;
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if (spi->mode & SPI_LOOP)
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cr |= XSPI_CR_LOOP;
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xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
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/* We do not check spi->max_speed_hz here as the SPI clock
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* frequency is not software programmable (the IP block design
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* parameter)
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*/
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cs = xspi->cs_inactive;
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cs ^= BIT(spi->chip_select);
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/* Activate the chip select */
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xspi->write_fn(cs, xspi->regs + XSPI_SSR_OFFSET);
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}
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/* spi_bitbang requires custom setup_transfer() to be defined if there is a
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* custom txrx_bufs().
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*/
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static int xilinx_spi_setup_transfer(struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
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if (spi->mode & SPI_CS_HIGH)
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xspi->cs_inactive &= ~BIT(spi->chip_select);
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else
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xspi->cs_inactive |= BIT(spi->chip_select);
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return 0;
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}
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static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
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{
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struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
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int remaining_words; /* the number of words left to transfer */
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bool use_irq = false;
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u16 cr = 0;
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/* We get here with transmitter inhibited */
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xspi->tx_ptr = t->tx_buf;
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xspi->rx_ptr = t->rx_buf;
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remaining_words = t->len / xspi->bytes_per_word;
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if (xspi->irq >= 0 && remaining_words > xspi->buffer_size) {
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u32 isr;
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use_irq = true;
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/* Inhibit irq to avoid spurious irqs on tx_empty*/
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cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
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xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
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xspi->regs + XSPI_CR_OFFSET);
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/* ACK old irqs (if any) */
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isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
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if (isr)
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xspi->write_fn(isr,
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xspi->regs + XIPIF_V123B_IISR_OFFSET);
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/* Enable the global IPIF interrupt */
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xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
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xspi->regs + XIPIF_V123B_DGIER_OFFSET);
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reinit_completion(&xspi->done);
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}
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while (remaining_words) {
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int n_words, tx_words, rx_words;
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u32 sr;
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int stalled;
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n_words = min(remaining_words, xspi->buffer_size);
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tx_words = n_words;
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while (tx_words--)
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xilinx_spi_tx(xspi);
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/* Start the transfer by not inhibiting the transmitter any
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* longer
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*/
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if (use_irq) {
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xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
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wait_for_completion(&xspi->done);
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/* A transmit has just completed. Process received data
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* and check for more data to transmit. Always inhibit
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* the transmitter while the Isr refills the transmit
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* register/FIFO, or make sure it is stopped if we're
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* done.
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*/
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xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
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xspi->regs + XSPI_CR_OFFSET);
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sr = XSPI_SR_TX_EMPTY_MASK;
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} else
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sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
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/* Read out all the data from the Rx FIFO */
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rx_words = n_words;
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stalled = 10;
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while (rx_words) {
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if (rx_words == n_words && !(stalled--) &&
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!(sr & XSPI_SR_TX_EMPTY_MASK) &&
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(sr & XSPI_SR_RX_EMPTY_MASK)) {
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dev_err(&spi->dev,
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"Detected stall. Check C_SPI_MODE and C_SPI_MEMORY\n");
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xspi_init_hw(xspi);
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return -EIO;
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}
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if ((sr & XSPI_SR_TX_EMPTY_MASK) && (rx_words > 1)) {
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xilinx_spi_rx(xspi);
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rx_words--;
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continue;
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}
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sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
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if (!(sr & XSPI_SR_RX_EMPTY_MASK)) {
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xilinx_spi_rx(xspi);
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rx_words--;
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}
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}
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remaining_words -= n_words;
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}
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if (use_irq) {
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xspi->write_fn(0, xspi->regs + XIPIF_V123B_DGIER_OFFSET);
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xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
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}
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return t->len;
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}
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/* This driver supports single master mode only. Hence Tx FIFO Empty
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* is the only interrupt we care about.
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* Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
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* Fault are not to happen.
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*/
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static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
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{
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struct xilinx_spi *xspi = dev_id;
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u32 ipif_isr;
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/* Get the IPIF interrupts, and clear them immediately */
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ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
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xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
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if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */
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complete(&xspi->done);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static int xilinx_spi_find_buffer_size(struct xilinx_spi *xspi)
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{
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u8 sr;
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int n_words = 0;
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/*
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* Before the buffer_size detection we reset the core
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* to make sure we start with a clean state.
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*/
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xspi->write_fn(XIPIF_V123B_RESET_MASK,
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xspi->regs + XIPIF_V123B_RESETR_OFFSET);
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/* Fill the Tx FIFO with as many words as possible */
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do {
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xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
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sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
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n_words++;
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} while (!(sr & XSPI_SR_TX_FULL_MASK));
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return n_words;
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}
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static const struct of_device_id xilinx_spi_of_match[] = {
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{ .compatible = "xlnx,axi-quad-spi-1.00.a", },
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{ .compatible = "xlnx,xps-spi-2.00.a", },
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{ .compatible = "xlnx,xps-spi-2.00.b", },
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{}
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};
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MODULE_DEVICE_TABLE(of, xilinx_spi_of_match);
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static int xilinx_spi_probe(struct platform_device *pdev)
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{
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struct xilinx_spi *xspi;
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struct xspi_platform_data *pdata;
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struct resource *res;
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int ret, num_cs = 0, bits_per_word = 8;
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struct spi_master *master;
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u32 tmp;
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u8 i;
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pdata = dev_get_platdata(&pdev->dev);
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if (pdata) {
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num_cs = pdata->num_chipselect;
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bits_per_word = pdata->bits_per_word;
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} else {
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of_property_read_u32(pdev->dev.of_node, "xlnx,num-ss-bits",
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&num_cs);
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}
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if (!num_cs) {
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dev_err(&pdev->dev,
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"Missing slave select configuration data\n");
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return -EINVAL;
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}
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if (num_cs > XILINX_SPI_MAX_CS) {
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dev_err(&pdev->dev, "Invalid number of spi slaves\n");
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return -EINVAL;
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}
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master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi));
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if (!master)
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return -ENODEV;
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/* the spi->mode bits understood by this driver: */
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master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP |
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SPI_CS_HIGH;
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xspi = spi_master_get_devdata(master);
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xspi->cs_inactive = 0xffffffff;
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xspi->bitbang.master = master;
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xspi->bitbang.chipselect = xilinx_spi_chipselect;
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xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
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xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
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init_completion(&xspi->done);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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xspi->regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(xspi->regs)) {
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ret = PTR_ERR(xspi->regs);
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goto put_master;
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}
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master->bus_num = pdev->id;
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master->num_chipselect = num_cs;
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master->dev.of_node = pdev->dev.of_node;
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/*
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* Detect endianess on the IP via loop bit in CR. Detection
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* must be done before reset is sent because incorrect reset
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* value generates error interrupt.
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* Setup little endian helper functions first and try to use them
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* and check if bit was correctly setup or not.
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*/
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xspi->read_fn = xspi_read32;
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xspi->write_fn = xspi_write32;
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xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET);
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tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
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tmp &= XSPI_CR_LOOP;
|
|
if (tmp != XSPI_CR_LOOP) {
|
|
xspi->read_fn = xspi_read32_be;
|
|
xspi->write_fn = xspi_write32_be;
|
|
}
|
|
|
|
master->bits_per_word_mask = SPI_BPW_MASK(bits_per_word);
|
|
xspi->bytes_per_word = bits_per_word / 8;
|
|
xspi->buffer_size = xilinx_spi_find_buffer_size(xspi);
|
|
|
|
xspi->irq = platform_get_irq(pdev, 0);
|
|
if (xspi->irq < 0 && xspi->irq != -ENXIO) {
|
|
ret = xspi->irq;
|
|
goto put_master;
|
|
} else if (xspi->irq >= 0) {
|
|
/* Register for SPI Interrupt */
|
|
ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0,
|
|
dev_name(&pdev->dev), xspi);
|
|
if (ret)
|
|
goto put_master;
|
|
}
|
|
|
|
/* SPI controller initializations */
|
|
xspi_init_hw(xspi);
|
|
|
|
ret = spi_bitbang_start(&xspi->bitbang);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "spi_bitbang_start FAILED\n");
|
|
goto put_master;
|
|
}
|
|
|
|
dev_info(&pdev->dev, "at 0x%08llX mapped to 0x%p, irq=%d\n",
|
|
(unsigned long long)res->start, xspi->regs, xspi->irq);
|
|
|
|
if (pdata) {
|
|
for (i = 0; i < pdata->num_devices; i++)
|
|
spi_new_device(master, pdata->devices + i);
|
|
}
|
|
|
|
platform_set_drvdata(pdev, master);
|
|
return 0;
|
|
|
|
put_master:
|
|
spi_master_put(master);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int xilinx_spi_remove(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master = platform_get_drvdata(pdev);
|
|
struct xilinx_spi *xspi = spi_master_get_devdata(master);
|
|
void __iomem *regs_base = xspi->regs;
|
|
|
|
spi_bitbang_stop(&xspi->bitbang);
|
|
|
|
/* Disable all the interrupts just in case */
|
|
xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
|
|
/* Disable the global IPIF interrupt */
|
|
xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
|
|
|
|
spi_master_put(xspi->bitbang.master);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* work with hotplug and coldplug */
|
|
MODULE_ALIAS("platform:" XILINX_SPI_NAME);
|
|
|
|
static struct platform_driver xilinx_spi_driver = {
|
|
.probe = xilinx_spi_probe,
|
|
.remove = xilinx_spi_remove,
|
|
.driver = {
|
|
.name = XILINX_SPI_NAME,
|
|
.of_match_table = xilinx_spi_of_match,
|
|
},
|
|
};
|
|
module_platform_driver(xilinx_spi_driver);
|
|
|
|
MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
|
|
MODULE_DESCRIPTION("Xilinx SPI driver");
|
|
MODULE_LICENSE("GPL");
|