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7c2861a6fb
The driver does not disable ref_clk on remove. According to the comment, the only reason to enable the clock is to get its rate. So, it should be safe to disable clk just after that. By the way, clk_prepare_enable() looks to be more appropriate than clk_enable() here. Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by: Alexey Khoroshilov <khoroshilov@ispras.ru> Signed-off-by: Mark Brown <broonie@kernel.org>
234 lines
5.3 KiB
C
234 lines
5.3 KiB
C
/*
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* J-Core SPI controller driver
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*
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* Copyright (C) 2012-2016 Smart Energy Instruments, Inc.
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*
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* Current version by Rich Felker
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* Based loosely on initial version by Oleksandr G Zhadan
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*
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/errno.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/delay.h>
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#define DRV_NAME "jcore_spi"
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#define CTRL_REG 0x0
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#define DATA_REG 0x4
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#define JCORE_SPI_CTRL_XMIT 0x02
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#define JCORE_SPI_STAT_BUSY 0x02
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#define JCORE_SPI_CTRL_LOOP 0x08
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#define JCORE_SPI_CTRL_CS_BITS 0x15
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#define JCORE_SPI_WAIT_RDY_MAX_LOOP 2000000
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struct jcore_spi {
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struct spi_master *master;
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void __iomem *base;
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unsigned int cs_reg;
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unsigned int speed_reg;
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unsigned int speed_hz;
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unsigned int clock_freq;
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};
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static int jcore_spi_wait(void __iomem *ctrl_reg)
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{
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unsigned timeout = JCORE_SPI_WAIT_RDY_MAX_LOOP;
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do {
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if (!(readl(ctrl_reg) & JCORE_SPI_STAT_BUSY))
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return 0;
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cpu_relax();
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} while (--timeout);
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return -EBUSY;
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}
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static void jcore_spi_program(struct jcore_spi *hw)
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{
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void __iomem *ctrl_reg = hw->base + CTRL_REG;
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if (jcore_spi_wait(ctrl_reg))
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dev_err(hw->master->dev.parent,
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"timeout waiting to program ctrl reg.\n");
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writel(hw->cs_reg | hw->speed_reg, ctrl_reg);
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}
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static void jcore_spi_chipsel(struct spi_device *spi, bool value)
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{
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struct jcore_spi *hw = spi_master_get_devdata(spi->master);
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u32 csbit = 1U << (2 * spi->chip_select);
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dev_dbg(hw->master->dev.parent, "chipselect %d\n", spi->chip_select);
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if (value)
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hw->cs_reg |= csbit;
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else
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hw->cs_reg &= ~csbit;
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jcore_spi_program(hw);
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}
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static void jcore_spi_baudrate(struct jcore_spi *hw, int speed)
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{
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if (speed == hw->speed_hz) return;
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hw->speed_hz = speed;
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if (speed >= hw->clock_freq / 2)
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hw->speed_reg = 0;
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else
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hw->speed_reg = ((hw->clock_freq / 2 / speed) - 1) << 27;
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jcore_spi_program(hw);
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dev_dbg(hw->master->dev.parent, "speed=%d reg=0x%x\n",
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speed, hw->speed_reg);
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}
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static int jcore_spi_txrx(struct spi_master *master, struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct jcore_spi *hw = spi_master_get_devdata(master);
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void __iomem *ctrl_reg = hw->base + CTRL_REG;
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void __iomem *data_reg = hw->base + DATA_REG;
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u32 xmit;
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/* data buffers */
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const unsigned char *tx;
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unsigned char *rx;
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unsigned int len;
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unsigned int count;
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jcore_spi_baudrate(hw, t->speed_hz);
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xmit = hw->cs_reg | hw->speed_reg | JCORE_SPI_CTRL_XMIT;
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tx = t->tx_buf;
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rx = t->rx_buf;
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len = t->len;
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for (count = 0; count < len; count++) {
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if (jcore_spi_wait(ctrl_reg))
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break;
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writel(tx ? *tx++ : 0, data_reg);
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writel(xmit, ctrl_reg);
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if (jcore_spi_wait(ctrl_reg))
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break;
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if (rx)
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*rx++ = readl(data_reg);
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}
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spi_finalize_current_transfer(master);
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if (count < len)
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return -EREMOTEIO;
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return 0;
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}
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static int jcore_spi_probe(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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struct jcore_spi *hw;
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struct spi_master *master;
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struct resource *res;
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u32 clock_freq;
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struct clk *clk;
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int err = -ENODEV;
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master = spi_alloc_master(&pdev->dev, sizeof(struct jcore_spi));
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if (!master)
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return err;
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/* Setup the master state. */
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master->num_chipselect = 3;
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master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
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master->transfer_one = jcore_spi_txrx;
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master->set_cs = jcore_spi_chipsel;
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master->dev.of_node = node;
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master->bus_num = pdev->id;
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hw = spi_master_get_devdata(master);
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hw->master = master;
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platform_set_drvdata(pdev, hw);
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/* Find and map our resources */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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goto exit_busy;
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if (!devm_request_mem_region(&pdev->dev, res->start,
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resource_size(res), pdev->name))
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goto exit_busy;
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hw->base = devm_ioremap_nocache(&pdev->dev, res->start,
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resource_size(res));
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if (!hw->base)
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goto exit_busy;
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/*
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* The SPI clock rate controlled via a configurable clock divider
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* which is applied to the reference clock. A 50 MHz reference is
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* most suitable for obtaining standard SPI clock rates, but some
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* designs may have a different reference clock, and the DT must
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* make the driver aware so that it can properly program the
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* requested rate. If the clock is omitted, 50 MHz is assumed.
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*/
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clock_freq = 50000000;
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clk = devm_clk_get(&pdev->dev, "ref_clk");
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if (!IS_ERR(clk)) {
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if (clk_prepare_enable(clk) == 0) {
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clock_freq = clk_get_rate(clk);
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clk_disable_unprepare(clk);
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} else
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dev_warn(&pdev->dev, "could not enable ref_clk\n");
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}
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hw->clock_freq = clock_freq;
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/* Initialize all CS bits to high. */
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hw->cs_reg = JCORE_SPI_CTRL_CS_BITS;
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jcore_spi_baudrate(hw, 400000);
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/* Register our spi controller */
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err = devm_spi_register_master(&pdev->dev, master);
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if (err)
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goto exit;
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return 0;
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exit_busy:
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err = -EBUSY;
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exit:
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spi_master_put(master);
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return err;
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}
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static const struct of_device_id jcore_spi_of_match[] = {
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{ .compatible = "jcore,spi2" },
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{},
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};
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MODULE_DEVICE_TABLE(of, jcore_spi_of_match);
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static struct platform_driver jcore_spi_driver = {
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.probe = jcore_spi_probe,
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.driver = {
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.name = DRV_NAME,
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.of_match_table = jcore_spi_of_match,
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},
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};
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module_platform_driver(jcore_spi_driver);
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MODULE_DESCRIPTION("J-Core SPI driver");
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MODULE_AUTHOR("Rich Felker <dalias@libc.org>");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:" DRV_NAME);
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