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0beb0a6da8
SPI core validates both bits_per_word and speed_hz transfer parameters and defaults to spi->bits_per_word and spi->max_speed_hz in case these per transfer parameters are not set. This can simplify a little the au1550_spi_setupxfer() as there is need to check only for valid "struct spi_transfer" pointer. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
1002 lines
26 KiB
C
1002 lines
26 KiB
C
/*
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* au1550 psc spi controller driver
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* may work also with au1200, au1210, au1250
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* will not work on au1000, au1100 and au1500 (no full spi controller there)
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*
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* Copyright (c) 2006 ATRON electronic GmbH
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* Author: Jan Nikitenko <jan.nikitenko@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/errno.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/resource.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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#include <linux/dma-mapping.h>
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#include <linux/completion.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-au1x00/au1xxx_psc.h>
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#include <asm/mach-au1x00/au1xxx_dbdma.h>
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#include <asm/mach-au1x00/au1550_spi.h>
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static unsigned usedma = 1;
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module_param(usedma, uint, 0644);
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/*
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#define AU1550_SPI_DEBUG_LOOPBACK
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*/
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#define AU1550_SPI_DBDMA_DESCRIPTORS 1
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#define AU1550_SPI_DMA_RXTMP_MINSIZE 2048U
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struct au1550_spi {
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struct spi_bitbang bitbang;
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volatile psc_spi_t __iomem *regs;
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int irq;
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unsigned len;
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unsigned tx_count;
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unsigned rx_count;
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const u8 *tx;
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u8 *rx;
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void (*rx_word)(struct au1550_spi *hw);
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void (*tx_word)(struct au1550_spi *hw);
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int (*txrx_bufs)(struct spi_device *spi, struct spi_transfer *t);
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irqreturn_t (*irq_callback)(struct au1550_spi *hw);
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struct completion master_done;
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unsigned usedma;
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u32 dma_tx_id;
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u32 dma_rx_id;
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u32 dma_tx_ch;
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u32 dma_rx_ch;
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u8 *dma_rx_tmpbuf;
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unsigned dma_rx_tmpbuf_size;
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u32 dma_rx_tmpbuf_addr;
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struct spi_master *master;
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struct device *dev;
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struct au1550_spi_info *pdata;
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struct resource *ioarea;
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};
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/* we use an 8-bit memory device for dma transfers to/from spi fifo */
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static dbdev_tab_t au1550_spi_mem_dbdev =
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{
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.dev_id = DBDMA_MEM_CHAN,
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.dev_flags = DEV_FLAGS_ANYUSE|DEV_FLAGS_SYNC,
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.dev_tsize = 0,
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.dev_devwidth = 8,
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.dev_physaddr = 0x00000000,
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.dev_intlevel = 0,
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.dev_intpolarity = 0
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};
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static int ddma_memid; /* id to above mem dma device */
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static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw);
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/*
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* compute BRG and DIV bits to setup spi clock based on main input clock rate
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* that was specified in platform data structure
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* according to au1550 datasheet:
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* psc_tempclk = psc_mainclk / (2 << DIV)
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* spiclk = psc_tempclk / (2 * (BRG + 1))
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* BRG valid range is 4..63
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* DIV valid range is 0..3
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*/
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static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned speed_hz)
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{
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u32 mainclk_hz = hw->pdata->mainclk_hz;
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u32 div, brg;
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for (div = 0; div < 4; div++) {
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brg = mainclk_hz / speed_hz / (4 << div);
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/* now we have BRG+1 in brg, so count with that */
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if (brg < (4 + 1)) {
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brg = (4 + 1); /* speed_hz too big */
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break; /* set lowest brg (div is == 0) */
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}
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if (brg <= (63 + 1))
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break; /* we have valid brg and div */
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}
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if (div == 4) {
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div = 3; /* speed_hz too small */
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brg = (63 + 1); /* set highest brg and div */
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}
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brg--;
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return PSC_SPICFG_SET_BAUD(brg) | PSC_SPICFG_SET_DIV(div);
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}
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static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw)
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{
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hw->regs->psc_spimsk =
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PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO
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| PSC_SPIMSK_RU | PSC_SPIMSK_TR | PSC_SPIMSK_TO
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| PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD;
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wmb(); /* drain writebuffer */
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hw->regs->psc_spievent =
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PSC_SPIEVNT_MM | PSC_SPIEVNT_RR | PSC_SPIEVNT_RO
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| PSC_SPIEVNT_RU | PSC_SPIEVNT_TR | PSC_SPIEVNT_TO
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| PSC_SPIEVNT_TU | PSC_SPIEVNT_SD | PSC_SPIEVNT_MD;
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wmb(); /* drain writebuffer */
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}
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static void au1550_spi_reset_fifos(struct au1550_spi *hw)
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{
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u32 pcr;
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hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC;
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wmb(); /* drain writebuffer */
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do {
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pcr = hw->regs->psc_spipcr;
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wmb(); /* drain writebuffer */
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} while (pcr != 0);
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}
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/*
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* dma transfers are used for the most common spi word size of 8-bits
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* we cannot easily change already set up dma channels' width, so if we wanted
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* dma support for more than 8-bit words (up to 24 bits), we would need to
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* setup dma channels from scratch on each spi transfer, based on bits_per_word
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* instead we have pre set up 8 bit dma channels supporting spi 4 to 8 bits
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* transfers, and 9 to 24 bits spi transfers will be done in pio irq based mode
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* callbacks to handle dma or pio are set up in au1550_spi_bits_handlers_set()
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*/
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static void au1550_spi_chipsel(struct spi_device *spi, int value)
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{
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struct au1550_spi *hw = spi_master_get_devdata(spi->master);
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unsigned cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
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u32 cfg, stat;
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switch (value) {
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case BITBANG_CS_INACTIVE:
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if (hw->pdata->deactivate_cs)
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hw->pdata->deactivate_cs(hw->pdata, spi->chip_select,
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cspol);
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break;
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case BITBANG_CS_ACTIVE:
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au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
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cfg = hw->regs->psc_spicfg;
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wmb(); /* drain writebuffer */
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hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
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wmb(); /* drain writebuffer */
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if (spi->mode & SPI_CPOL)
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cfg |= PSC_SPICFG_BI;
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else
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cfg &= ~PSC_SPICFG_BI;
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if (spi->mode & SPI_CPHA)
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cfg &= ~PSC_SPICFG_CDE;
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else
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cfg |= PSC_SPICFG_CDE;
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if (spi->mode & SPI_LSB_FIRST)
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cfg |= PSC_SPICFG_MLF;
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else
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cfg &= ~PSC_SPICFG_MLF;
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if (hw->usedma && spi->bits_per_word <= 8)
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cfg &= ~PSC_SPICFG_DD_DISABLE;
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else
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cfg |= PSC_SPICFG_DD_DISABLE;
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cfg = PSC_SPICFG_CLR_LEN(cfg);
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cfg |= PSC_SPICFG_SET_LEN(spi->bits_per_word);
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cfg = PSC_SPICFG_CLR_BAUD(cfg);
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cfg &= ~PSC_SPICFG_SET_DIV(3);
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cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz);
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hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE;
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wmb(); /* drain writebuffer */
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do {
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stat = hw->regs->psc_spistat;
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wmb(); /* drain writebuffer */
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} while ((stat & PSC_SPISTAT_DR) == 0);
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if (hw->pdata->activate_cs)
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hw->pdata->activate_cs(hw->pdata, spi->chip_select,
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cspol);
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break;
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}
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}
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static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
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{
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struct au1550_spi *hw = spi_master_get_devdata(spi->master);
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unsigned bpw, hz;
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u32 cfg, stat;
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if (t) {
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bpw = t->bits_per_word;
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hz = t->speed_hz;
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} else {
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bpw = spi->bits_per_word;
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hz = spi->max_speed_hz;
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}
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if (!hz)
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return -EINVAL;
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au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
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cfg = hw->regs->psc_spicfg;
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wmb(); /* drain writebuffer */
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hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
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wmb(); /* drain writebuffer */
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if (hw->usedma && bpw <= 8)
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cfg &= ~PSC_SPICFG_DD_DISABLE;
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else
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cfg |= PSC_SPICFG_DD_DISABLE;
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cfg = PSC_SPICFG_CLR_LEN(cfg);
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cfg |= PSC_SPICFG_SET_LEN(bpw);
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cfg = PSC_SPICFG_CLR_BAUD(cfg);
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cfg &= ~PSC_SPICFG_SET_DIV(3);
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cfg |= au1550_spi_baudcfg(hw, hz);
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hw->regs->psc_spicfg = cfg;
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wmb(); /* drain writebuffer */
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if (cfg & PSC_SPICFG_DE_ENABLE) {
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do {
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stat = hw->regs->psc_spistat;
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wmb(); /* drain writebuffer */
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} while ((stat & PSC_SPISTAT_DR) == 0);
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}
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au1550_spi_reset_fifos(hw);
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au1550_spi_mask_ack_all(hw);
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return 0;
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}
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/*
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* for dma spi transfers, we have to setup rx channel, otherwise there is
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* no reliable way how to recognize that spi transfer is done
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* dma complete callbacks are called before real spi transfer is finished
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* and if only tx dma channel is set up (and rx fifo overflow event masked)
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* spi master done event irq is not generated unless rx fifo is empty (emptied)
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* so we need rx tmp buffer to use for rx dma if user does not provide one
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*/
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static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned size)
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{
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hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL);
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if (!hw->dma_rx_tmpbuf)
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return -ENOMEM;
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hw->dma_rx_tmpbuf_size = size;
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hw->dma_rx_tmpbuf_addr = dma_map_single(hw->dev, hw->dma_rx_tmpbuf,
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size, DMA_FROM_DEVICE);
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if (dma_mapping_error(hw->dev, hw->dma_rx_tmpbuf_addr)) {
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kfree(hw->dma_rx_tmpbuf);
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hw->dma_rx_tmpbuf = 0;
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hw->dma_rx_tmpbuf_size = 0;
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return -EFAULT;
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}
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return 0;
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}
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static void au1550_spi_dma_rxtmp_free(struct au1550_spi *hw)
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{
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dma_unmap_single(hw->dev, hw->dma_rx_tmpbuf_addr,
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hw->dma_rx_tmpbuf_size, DMA_FROM_DEVICE);
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kfree(hw->dma_rx_tmpbuf);
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hw->dma_rx_tmpbuf = 0;
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hw->dma_rx_tmpbuf_size = 0;
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}
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static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t)
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{
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struct au1550_spi *hw = spi_master_get_devdata(spi->master);
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dma_addr_t dma_tx_addr;
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dma_addr_t dma_rx_addr;
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u32 res;
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hw->len = t->len;
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hw->tx_count = 0;
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hw->rx_count = 0;
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hw->tx = t->tx_buf;
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hw->rx = t->rx_buf;
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dma_tx_addr = t->tx_dma;
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dma_rx_addr = t->rx_dma;
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/*
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* check if buffers are already dma mapped, map them otherwise:
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* - first map the TX buffer, so cache data gets written to memory
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* - then map the RX buffer, so that cache entries (with
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* soon-to-be-stale data) get removed
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* use rx buffer in place of tx if tx buffer was not provided
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* use temp rx buffer (preallocated or realloc to fit) for rx dma
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*/
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if (t->tx_buf) {
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if (t->tx_dma == 0) { /* if DMA_ADDR_INVALID, map it */
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dma_tx_addr = dma_map_single(hw->dev,
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(void *)t->tx_buf,
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t->len, DMA_TO_DEVICE);
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if (dma_mapping_error(hw->dev, dma_tx_addr))
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dev_err(hw->dev, "tx dma map error\n");
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}
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}
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if (t->rx_buf) {
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if (t->rx_dma == 0) { /* if DMA_ADDR_INVALID, map it */
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dma_rx_addr = dma_map_single(hw->dev,
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(void *)t->rx_buf,
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t->len, DMA_FROM_DEVICE);
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if (dma_mapping_error(hw->dev, dma_rx_addr))
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dev_err(hw->dev, "rx dma map error\n");
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}
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} else {
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if (t->len > hw->dma_rx_tmpbuf_size) {
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int ret;
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au1550_spi_dma_rxtmp_free(hw);
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ret = au1550_spi_dma_rxtmp_alloc(hw, max(t->len,
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AU1550_SPI_DMA_RXTMP_MINSIZE));
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if (ret < 0)
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return ret;
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}
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hw->rx = hw->dma_rx_tmpbuf;
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dma_rx_addr = hw->dma_rx_tmpbuf_addr;
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dma_sync_single_for_device(hw->dev, dma_rx_addr,
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t->len, DMA_FROM_DEVICE);
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}
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if (!t->tx_buf) {
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dma_sync_single_for_device(hw->dev, dma_rx_addr,
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t->len, DMA_BIDIRECTIONAL);
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hw->tx = hw->rx;
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}
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/* put buffers on the ring */
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res = au1xxx_dbdma_put_dest(hw->dma_rx_ch, virt_to_phys(hw->rx),
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t->len, DDMA_FLAGS_IE);
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if (!res)
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dev_err(hw->dev, "rx dma put dest error\n");
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res = au1xxx_dbdma_put_source(hw->dma_tx_ch, virt_to_phys(hw->tx),
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t->len, DDMA_FLAGS_IE);
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if (!res)
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dev_err(hw->dev, "tx dma put source error\n");
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au1xxx_dbdma_start(hw->dma_rx_ch);
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au1xxx_dbdma_start(hw->dma_tx_ch);
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/* by default enable nearly all events interrupt */
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hw->regs->psc_spimsk = PSC_SPIMSK_SD;
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wmb(); /* drain writebuffer */
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/* start the transfer */
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hw->regs->psc_spipcr = PSC_SPIPCR_MS;
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wmb(); /* drain writebuffer */
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wait_for_completion(&hw->master_done);
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au1xxx_dbdma_stop(hw->dma_tx_ch);
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au1xxx_dbdma_stop(hw->dma_rx_ch);
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if (!t->rx_buf) {
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/* using the temporal preallocated and premapped buffer */
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dma_sync_single_for_cpu(hw->dev, dma_rx_addr, t->len,
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DMA_FROM_DEVICE);
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}
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/* unmap buffers if mapped above */
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if (t->rx_buf && t->rx_dma == 0 )
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dma_unmap_single(hw->dev, dma_rx_addr, t->len,
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DMA_FROM_DEVICE);
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if (t->tx_buf && t->tx_dma == 0 )
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dma_unmap_single(hw->dev, dma_tx_addr, t->len,
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DMA_TO_DEVICE);
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return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
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}
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static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw)
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{
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u32 stat, evnt;
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stat = hw->regs->psc_spistat;
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evnt = hw->regs->psc_spievent;
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wmb(); /* drain writebuffer */
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if ((stat & PSC_SPISTAT_DI) == 0) {
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dev_err(hw->dev, "Unexpected IRQ!\n");
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return IRQ_NONE;
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}
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if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
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| PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
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| PSC_SPIEVNT_TU | PSC_SPIEVNT_SD))
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!= 0) {
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/*
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* due to an spi error we consider transfer as done,
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* so mask all events until before next transfer start
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* and stop the possibly running dma immediately
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*/
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au1550_spi_mask_ack_all(hw);
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au1xxx_dbdma_stop(hw->dma_rx_ch);
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au1xxx_dbdma_stop(hw->dma_tx_ch);
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/* get number of transferred bytes */
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hw->rx_count = hw->len - au1xxx_get_dma_residue(hw->dma_rx_ch);
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hw->tx_count = hw->len - au1xxx_get_dma_residue(hw->dma_tx_ch);
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au1xxx_dbdma_reset(hw->dma_rx_ch);
|
|
au1xxx_dbdma_reset(hw->dma_tx_ch);
|
|
au1550_spi_reset_fifos(hw);
|
|
|
|
if (evnt == PSC_SPIEVNT_RO)
|
|
dev_err(hw->dev,
|
|
"dma transfer: receive FIFO overflow!\n");
|
|
else
|
|
dev_err(hw->dev,
|
|
"dma transfer: unexpected SPI error "
|
|
"(event=0x%x stat=0x%x)!\n", evnt, stat);
|
|
|
|
complete(&hw->master_done);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
if ((evnt & PSC_SPIEVNT_MD) != 0) {
|
|
/* transfer completed successfully */
|
|
au1550_spi_mask_ack_all(hw);
|
|
hw->rx_count = hw->len;
|
|
hw->tx_count = hw->len;
|
|
complete(&hw->master_done);
|
|
}
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
|
|
/* routines to handle different word sizes in pio mode */
|
|
#define AU1550_SPI_RX_WORD(size, mask) \
|
|
static void au1550_spi_rx_word_##size(struct au1550_spi *hw) \
|
|
{ \
|
|
u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask); \
|
|
wmb(); /* drain writebuffer */ \
|
|
if (hw->rx) { \
|
|
*(u##size *)hw->rx = (u##size)fifoword; \
|
|
hw->rx += (size) / 8; \
|
|
} \
|
|
hw->rx_count += (size) / 8; \
|
|
}
|
|
|
|
#define AU1550_SPI_TX_WORD(size, mask) \
|
|
static void au1550_spi_tx_word_##size(struct au1550_spi *hw) \
|
|
{ \
|
|
u32 fifoword = 0; \
|
|
if (hw->tx) { \
|
|
fifoword = *(u##size *)hw->tx & (u32)(mask); \
|
|
hw->tx += (size) / 8; \
|
|
} \
|
|
hw->tx_count += (size) / 8; \
|
|
if (hw->tx_count >= hw->len) \
|
|
fifoword |= PSC_SPITXRX_LC; \
|
|
hw->regs->psc_spitxrx = fifoword; \
|
|
wmb(); /* drain writebuffer */ \
|
|
}
|
|
|
|
AU1550_SPI_RX_WORD(8,0xff)
|
|
AU1550_SPI_RX_WORD(16,0xffff)
|
|
AU1550_SPI_RX_WORD(32,0xffffff)
|
|
AU1550_SPI_TX_WORD(8,0xff)
|
|
AU1550_SPI_TX_WORD(16,0xffff)
|
|
AU1550_SPI_TX_WORD(32,0xffffff)
|
|
|
|
static int au1550_spi_pio_txrxb(struct spi_device *spi, struct spi_transfer *t)
|
|
{
|
|
u32 stat, mask;
|
|
struct au1550_spi *hw = spi_master_get_devdata(spi->master);
|
|
|
|
hw->tx = t->tx_buf;
|
|
hw->rx = t->rx_buf;
|
|
hw->len = t->len;
|
|
hw->tx_count = 0;
|
|
hw->rx_count = 0;
|
|
|
|
/* by default enable nearly all events after filling tx fifo */
|
|
mask = PSC_SPIMSK_SD;
|
|
|
|
/* fill the transmit FIFO */
|
|
while (hw->tx_count < hw->len) {
|
|
|
|
hw->tx_word(hw);
|
|
|
|
if (hw->tx_count >= hw->len) {
|
|
/* mask tx fifo request interrupt as we are done */
|
|
mask |= PSC_SPIMSK_TR;
|
|
}
|
|
|
|
stat = hw->regs->psc_spistat;
|
|
wmb(); /* drain writebuffer */
|
|
if (stat & PSC_SPISTAT_TF)
|
|
break;
|
|
}
|
|
|
|
/* enable event interrupts */
|
|
hw->regs->psc_spimsk = mask;
|
|
wmb(); /* drain writebuffer */
|
|
|
|
/* start the transfer */
|
|
hw->regs->psc_spipcr = PSC_SPIPCR_MS;
|
|
wmb(); /* drain writebuffer */
|
|
|
|
wait_for_completion(&hw->master_done);
|
|
|
|
return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
|
|
}
|
|
|
|
static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
|
|
{
|
|
int busy;
|
|
u32 stat, evnt;
|
|
|
|
stat = hw->regs->psc_spistat;
|
|
evnt = hw->regs->psc_spievent;
|
|
wmb(); /* drain writebuffer */
|
|
if ((stat & PSC_SPISTAT_DI) == 0) {
|
|
dev_err(hw->dev, "Unexpected IRQ!\n");
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
|
|
| PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
|
|
| PSC_SPIEVNT_SD))
|
|
!= 0) {
|
|
/*
|
|
* due to an error we consider transfer as done,
|
|
* so mask all events until before next transfer start
|
|
*/
|
|
au1550_spi_mask_ack_all(hw);
|
|
au1550_spi_reset_fifos(hw);
|
|
dev_err(hw->dev,
|
|
"pio transfer: unexpected SPI error "
|
|
"(event=0x%x stat=0x%x)!\n", evnt, stat);
|
|
complete(&hw->master_done);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
/*
|
|
* while there is something to read from rx fifo
|
|
* or there is a space to write to tx fifo:
|
|
*/
|
|
do {
|
|
busy = 0;
|
|
stat = hw->regs->psc_spistat;
|
|
wmb(); /* drain writebuffer */
|
|
|
|
/*
|
|
* Take care to not let the Rx FIFO overflow.
|
|
*
|
|
* We only write a byte if we have read one at least. Initially,
|
|
* the write fifo is full, so we should read from the read fifo
|
|
* first.
|
|
* In case we miss a word from the read fifo, we should get a
|
|
* RO event and should back out.
|
|
*/
|
|
if (!(stat & PSC_SPISTAT_RE) && hw->rx_count < hw->len) {
|
|
hw->rx_word(hw);
|
|
busy = 1;
|
|
|
|
if (!(stat & PSC_SPISTAT_TF) && hw->tx_count < hw->len)
|
|
hw->tx_word(hw);
|
|
}
|
|
} while (busy);
|
|
|
|
hw->regs->psc_spievent = PSC_SPIEVNT_RR | PSC_SPIEVNT_TR;
|
|
wmb(); /* drain writebuffer */
|
|
|
|
/*
|
|
* Restart the SPI transmission in case of a transmit underflow.
|
|
* This seems to work despite the notes in the Au1550 data book
|
|
* of Figure 8-4 with flowchart for SPI master operation:
|
|
*
|
|
* """Note 1: An XFR Error Interrupt occurs, unless masked,
|
|
* for any of the following events: Tx FIFO Underflow,
|
|
* Rx FIFO Overflow, or Multiple-master Error
|
|
* Note 2: In case of a Tx Underflow Error, all zeroes are
|
|
* transmitted."""
|
|
*
|
|
* By simply restarting the spi transfer on Tx Underflow Error,
|
|
* we assume that spi transfer was paused instead of zeroes
|
|
* transmittion mentioned in the Note 2 of Au1550 data book.
|
|
*/
|
|
if (evnt & PSC_SPIEVNT_TU) {
|
|
hw->regs->psc_spievent = PSC_SPIEVNT_TU | PSC_SPIEVNT_MD;
|
|
wmb(); /* drain writebuffer */
|
|
hw->regs->psc_spipcr = PSC_SPIPCR_MS;
|
|
wmb(); /* drain writebuffer */
|
|
}
|
|
|
|
if (hw->rx_count >= hw->len) {
|
|
/* transfer completed successfully */
|
|
au1550_spi_mask_ack_all(hw);
|
|
complete(&hw->master_done);
|
|
}
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int au1550_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
|
|
{
|
|
struct au1550_spi *hw = spi_master_get_devdata(spi->master);
|
|
return hw->txrx_bufs(spi, t);
|
|
}
|
|
|
|
static irqreturn_t au1550_spi_irq(int irq, void *dev)
|
|
{
|
|
struct au1550_spi *hw = dev;
|
|
return hw->irq_callback(hw);
|
|
}
|
|
|
|
static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw)
|
|
{
|
|
if (bpw <= 8) {
|
|
if (hw->usedma) {
|
|
hw->txrx_bufs = &au1550_spi_dma_txrxb;
|
|
hw->irq_callback = &au1550_spi_dma_irq_callback;
|
|
} else {
|
|
hw->rx_word = &au1550_spi_rx_word_8;
|
|
hw->tx_word = &au1550_spi_tx_word_8;
|
|
hw->txrx_bufs = &au1550_spi_pio_txrxb;
|
|
hw->irq_callback = &au1550_spi_pio_irq_callback;
|
|
}
|
|
} else if (bpw <= 16) {
|
|
hw->rx_word = &au1550_spi_rx_word_16;
|
|
hw->tx_word = &au1550_spi_tx_word_16;
|
|
hw->txrx_bufs = &au1550_spi_pio_txrxb;
|
|
hw->irq_callback = &au1550_spi_pio_irq_callback;
|
|
} else {
|
|
hw->rx_word = &au1550_spi_rx_word_32;
|
|
hw->tx_word = &au1550_spi_tx_word_32;
|
|
hw->txrx_bufs = &au1550_spi_pio_txrxb;
|
|
hw->irq_callback = &au1550_spi_pio_irq_callback;
|
|
}
|
|
}
|
|
|
|
static void au1550_spi_setup_psc_as_spi(struct au1550_spi *hw)
|
|
{
|
|
u32 stat, cfg;
|
|
|
|
/* set up the PSC for SPI mode */
|
|
hw->regs->psc_ctrl = PSC_CTRL_DISABLE;
|
|
wmb(); /* drain writebuffer */
|
|
hw->regs->psc_sel = PSC_SEL_PS_SPIMODE;
|
|
wmb(); /* drain writebuffer */
|
|
|
|
hw->regs->psc_spicfg = 0;
|
|
wmb(); /* drain writebuffer */
|
|
|
|
hw->regs->psc_ctrl = PSC_CTRL_ENABLE;
|
|
wmb(); /* drain writebuffer */
|
|
|
|
do {
|
|
stat = hw->regs->psc_spistat;
|
|
wmb(); /* drain writebuffer */
|
|
} while ((stat & PSC_SPISTAT_SR) == 0);
|
|
|
|
|
|
cfg = hw->usedma ? 0 : PSC_SPICFG_DD_DISABLE;
|
|
cfg |= PSC_SPICFG_SET_LEN(8);
|
|
cfg |= PSC_SPICFG_RT_FIFO8 | PSC_SPICFG_TT_FIFO8;
|
|
/* use minimal allowed brg and div values as initial setting: */
|
|
cfg |= PSC_SPICFG_SET_BAUD(4) | PSC_SPICFG_SET_DIV(0);
|
|
|
|
#ifdef AU1550_SPI_DEBUG_LOOPBACK
|
|
cfg |= PSC_SPICFG_LB;
|
|
#endif
|
|
|
|
hw->regs->psc_spicfg = cfg;
|
|
wmb(); /* drain writebuffer */
|
|
|
|
au1550_spi_mask_ack_all(hw);
|
|
|
|
hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE;
|
|
wmb(); /* drain writebuffer */
|
|
|
|
do {
|
|
stat = hw->regs->psc_spistat;
|
|
wmb(); /* drain writebuffer */
|
|
} while ((stat & PSC_SPISTAT_DR) == 0);
|
|
|
|
au1550_spi_reset_fifos(hw);
|
|
}
|
|
|
|
|
|
static int au1550_spi_probe(struct platform_device *pdev)
|
|
{
|
|
struct au1550_spi *hw;
|
|
struct spi_master *master;
|
|
struct resource *r;
|
|
int err = 0;
|
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof(struct au1550_spi));
|
|
if (master == NULL) {
|
|
dev_err(&pdev->dev, "No memory for spi_master\n");
|
|
err = -ENOMEM;
|
|
goto err_nomem;
|
|
}
|
|
|
|
/* the spi->mode bits understood by this driver: */
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
|
|
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 24);
|
|
|
|
hw = spi_master_get_devdata(master);
|
|
|
|
hw->master = master;
|
|
hw->pdata = dev_get_platdata(&pdev->dev);
|
|
hw->dev = &pdev->dev;
|
|
|
|
if (hw->pdata == NULL) {
|
|
dev_err(&pdev->dev, "No platform data supplied\n");
|
|
err = -ENOENT;
|
|
goto err_no_pdata;
|
|
}
|
|
|
|
r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
|
if (!r) {
|
|
dev_err(&pdev->dev, "no IRQ\n");
|
|
err = -ENODEV;
|
|
goto err_no_iores;
|
|
}
|
|
hw->irq = r->start;
|
|
|
|
hw->usedma = 0;
|
|
r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
|
|
if (r) {
|
|
hw->dma_tx_id = r->start;
|
|
r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
|
|
if (r) {
|
|
hw->dma_rx_id = r->start;
|
|
if (usedma && ddma_memid) {
|
|
if (pdev->dev.dma_mask == NULL)
|
|
dev_warn(&pdev->dev, "no dma mask\n");
|
|
else
|
|
hw->usedma = 1;
|
|
}
|
|
}
|
|
}
|
|
|
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!r) {
|
|
dev_err(&pdev->dev, "no mmio resource\n");
|
|
err = -ENODEV;
|
|
goto err_no_iores;
|
|
}
|
|
|
|
hw->ioarea = request_mem_region(r->start, sizeof(psc_spi_t),
|
|
pdev->name);
|
|
if (!hw->ioarea) {
|
|
dev_err(&pdev->dev, "Cannot reserve iomem region\n");
|
|
err = -ENXIO;
|
|
goto err_no_iores;
|
|
}
|
|
|
|
hw->regs = (psc_spi_t __iomem *)ioremap(r->start, sizeof(psc_spi_t));
|
|
if (!hw->regs) {
|
|
dev_err(&pdev->dev, "cannot ioremap\n");
|
|
err = -ENXIO;
|
|
goto err_ioremap;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, hw);
|
|
|
|
init_completion(&hw->master_done);
|
|
|
|
hw->bitbang.master = hw->master;
|
|
hw->bitbang.setup_transfer = au1550_spi_setupxfer;
|
|
hw->bitbang.chipselect = au1550_spi_chipsel;
|
|
hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs;
|
|
|
|
if (hw->usedma) {
|
|
hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(ddma_memid,
|
|
hw->dma_tx_id, NULL, (void *)hw);
|
|
if (hw->dma_tx_ch == 0) {
|
|
dev_err(&pdev->dev,
|
|
"Cannot allocate tx dma channel\n");
|
|
err = -ENXIO;
|
|
goto err_no_txdma;
|
|
}
|
|
au1xxx_dbdma_set_devwidth(hw->dma_tx_ch, 8);
|
|
if (au1xxx_dbdma_ring_alloc(hw->dma_tx_ch,
|
|
AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
|
|
dev_err(&pdev->dev,
|
|
"Cannot allocate tx dma descriptors\n");
|
|
err = -ENXIO;
|
|
goto err_no_txdma_descr;
|
|
}
|
|
|
|
|
|
hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id,
|
|
ddma_memid, NULL, (void *)hw);
|
|
if (hw->dma_rx_ch == 0) {
|
|
dev_err(&pdev->dev,
|
|
"Cannot allocate rx dma channel\n");
|
|
err = -ENXIO;
|
|
goto err_no_rxdma;
|
|
}
|
|
au1xxx_dbdma_set_devwidth(hw->dma_rx_ch, 8);
|
|
if (au1xxx_dbdma_ring_alloc(hw->dma_rx_ch,
|
|
AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
|
|
dev_err(&pdev->dev,
|
|
"Cannot allocate rx dma descriptors\n");
|
|
err = -ENXIO;
|
|
goto err_no_rxdma_descr;
|
|
}
|
|
|
|
err = au1550_spi_dma_rxtmp_alloc(hw,
|
|
AU1550_SPI_DMA_RXTMP_MINSIZE);
|
|
if (err < 0) {
|
|
dev_err(&pdev->dev,
|
|
"Cannot allocate initial rx dma tmp buffer\n");
|
|
goto err_dma_rxtmp_alloc;
|
|
}
|
|
}
|
|
|
|
au1550_spi_bits_handlers_set(hw, 8);
|
|
|
|
err = request_irq(hw->irq, au1550_spi_irq, 0, pdev->name, hw);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "Cannot claim IRQ\n");
|
|
goto err_no_irq;
|
|
}
|
|
|
|
master->bus_num = pdev->id;
|
|
master->num_chipselect = hw->pdata->num_chipselect;
|
|
|
|
/*
|
|
* precompute valid range for spi freq - from au1550 datasheet:
|
|
* psc_tempclk = psc_mainclk / (2 << DIV)
|
|
* spiclk = psc_tempclk / (2 * (BRG + 1))
|
|
* BRG valid range is 4..63
|
|
* DIV valid range is 0..3
|
|
* round the min and max frequencies to values that would still
|
|
* produce valid brg and div
|
|
*/
|
|
{
|
|
int min_div = (2 << 0) * (2 * (4 + 1));
|
|
int max_div = (2 << 3) * (2 * (63 + 1));
|
|
master->max_speed_hz = hw->pdata->mainclk_hz / min_div;
|
|
master->min_speed_hz =
|
|
hw->pdata->mainclk_hz / (max_div + 1) + 1;
|
|
}
|
|
|
|
au1550_spi_setup_psc_as_spi(hw);
|
|
|
|
err = spi_bitbang_start(&hw->bitbang);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "Failed to register SPI master\n");
|
|
goto err_register;
|
|
}
|
|
|
|
dev_info(&pdev->dev,
|
|
"spi master registered: bus_num=%d num_chipselect=%d\n",
|
|
master->bus_num, master->num_chipselect);
|
|
|
|
return 0;
|
|
|
|
err_register:
|
|
free_irq(hw->irq, hw);
|
|
|
|
err_no_irq:
|
|
au1550_spi_dma_rxtmp_free(hw);
|
|
|
|
err_dma_rxtmp_alloc:
|
|
err_no_rxdma_descr:
|
|
if (hw->usedma)
|
|
au1xxx_dbdma_chan_free(hw->dma_rx_ch);
|
|
|
|
err_no_rxdma:
|
|
err_no_txdma_descr:
|
|
if (hw->usedma)
|
|
au1xxx_dbdma_chan_free(hw->dma_tx_ch);
|
|
|
|
err_no_txdma:
|
|
iounmap((void __iomem *)hw->regs);
|
|
|
|
err_ioremap:
|
|
release_mem_region(r->start, sizeof(psc_spi_t));
|
|
|
|
err_no_iores:
|
|
err_no_pdata:
|
|
spi_master_put(hw->master);
|
|
|
|
err_nomem:
|
|
return err;
|
|
}
|
|
|
|
static int au1550_spi_remove(struct platform_device *pdev)
|
|
{
|
|
struct au1550_spi *hw = platform_get_drvdata(pdev);
|
|
|
|
dev_info(&pdev->dev, "spi master remove: bus_num=%d\n",
|
|
hw->master->bus_num);
|
|
|
|
spi_bitbang_stop(&hw->bitbang);
|
|
free_irq(hw->irq, hw);
|
|
iounmap((void __iomem *)hw->regs);
|
|
release_mem_region(hw->ioarea->start, sizeof(psc_spi_t));
|
|
|
|
if (hw->usedma) {
|
|
au1550_spi_dma_rxtmp_free(hw);
|
|
au1xxx_dbdma_chan_free(hw->dma_rx_ch);
|
|
au1xxx_dbdma_chan_free(hw->dma_tx_ch);
|
|
}
|
|
|
|
spi_master_put(hw->master);
|
|
return 0;
|
|
}
|
|
|
|
/* work with hotplug and coldplug */
|
|
MODULE_ALIAS("platform:au1550-spi");
|
|
|
|
static struct platform_driver au1550_spi_drv = {
|
|
.probe = au1550_spi_probe,
|
|
.remove = au1550_spi_remove,
|
|
.driver = {
|
|
.name = "au1550-spi",
|
|
},
|
|
};
|
|
|
|
static int __init au1550_spi_init(void)
|
|
{
|
|
/*
|
|
* create memory device with 8 bits dev_devwidth
|
|
* needed for proper byte ordering to spi fifo
|
|
*/
|
|
switch (alchemy_get_cputype()) {
|
|
case ALCHEMY_CPU_AU1550:
|
|
case ALCHEMY_CPU_AU1200:
|
|
case ALCHEMY_CPU_AU1300:
|
|
break;
|
|
default:
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (usedma) {
|
|
ddma_memid = au1xxx_ddma_add_device(&au1550_spi_mem_dbdev);
|
|
if (!ddma_memid)
|
|
printk(KERN_ERR "au1550-spi: cannot add memory"
|
|
"dbdma device\n");
|
|
}
|
|
return platform_driver_register(&au1550_spi_drv);
|
|
}
|
|
module_init(au1550_spi_init);
|
|
|
|
static void __exit au1550_spi_exit(void)
|
|
{
|
|
if (usedma && ddma_memid)
|
|
au1xxx_ddma_del_device(ddma_memid);
|
|
platform_driver_unregister(&au1550_spi_drv);
|
|
}
|
|
module_exit(au1550_spi_exit);
|
|
|
|
MODULE_DESCRIPTION("Au1550 PSC SPI Driver");
|
|
MODULE_AUTHOR("Jan Nikitenko <jan.nikitenko@gmail.com>");
|
|
MODULE_LICENSE("GPL");
|