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76b1a87b21
Instead of the PCI code needing to have code to determine the cacheline size of each processor, use the data the cpu identification code should have already determined during early boot. (The vendor checks are also incomplete, and don't take into account modern CPUs) I've been carrying a variant of this code in Fedora for a while, that prints debug information. There are a number of cases where we are currently setting the PCI cacheline size to 32 bytes, when the CPU cacheline size is 64 bytes. With this patch, we set them both the same. Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> |
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| .. | ||
| acpi.c | ||
| amd_bus.c | ||
| bus_numa.h | ||
| common.c | ||
| direct.c | ||
| early.c | ||
| fixup.c | ||
| i386.c | ||
| init.c | ||
| intel_bus.c | ||
| irq.c | ||
| legacy.c | ||
| Makefile | ||
| mmconfig_32.c | ||
| mmconfig_64.c | ||
| mmconfig-shared.c | ||
| numaq_32.c | ||
| olpc.c | ||
| pcbios.c | ||
| visws.c | ||