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59a68d4138
As with strlen(), the patches importing the updated str{n}cmp()
implementations were originally developed and tested before the
advent of CONFIG_KASAN_HW_TAGS, and have subsequently revealed
not to be MTE-safe. Since in-kernel MTE is still a rather niche
case, let it temporarily fall back to the generic C versions for
correctness until we can figure out the best fix.
Fixes: 758602c044 ("arm64: Import latest version of Cortex Strings' strcmp")
Fixes: 020b199bc7 ("arm64: Import latest version of Cortex Strings' strncmp")
Cc: <stable@vger.kernel.org> # 5.14.x
Reported-by: Branislav Rankov <branislav.rankov@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/34dc4d12eec0adae49b0ac927df642ed10089d40.1631890770.git.robin.murphy@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
177 lines
4.9 KiB
ArmAsm
177 lines
4.9 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2012-2021, Arm Limited.
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*
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* Adapted from the original at:
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* https://github.com/ARM-software/optimized-routines/blob/afd6244a1f8d9229/string/aarch64/strcmp.S
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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/* Assumptions:
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*
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* ARMv8-a, AArch64
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*/
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#define L(label) .L ## label
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#define REP8_01 0x0101010101010101
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#define REP8_7f 0x7f7f7f7f7f7f7f7f
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#define REP8_80 0x8080808080808080
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/* Parameters and result. */
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#define src1 x0
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#define src2 x1
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#define result x0
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/* Internal variables. */
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#define data1 x2
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#define data1w w2
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#define data2 x3
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#define data2w w3
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#define has_nul x4
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#define diff x5
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#define syndrome x6
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#define tmp1 x7
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#define tmp2 x8
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#define tmp3 x9
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#define zeroones x10
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#define pos x11
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/* Start of performance-critical section -- one 64B cache line. */
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.align 6
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SYM_FUNC_START_WEAK_PI(strcmp)
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eor tmp1, src1, src2
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mov zeroones, #REP8_01
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tst tmp1, #7
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b.ne L(misaligned8)
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ands tmp1, src1, #7
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b.ne L(mutual_align)
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/* NUL detection works on the principle that (X - 1) & (~X) & 0x80
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(=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
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can be done in parallel across the entire word. */
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L(loop_aligned):
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ldr data1, [src1], #8
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ldr data2, [src2], #8
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L(start_realigned):
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sub tmp1, data1, zeroones
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orr tmp2, data1, #REP8_7f
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eor diff, data1, data2 /* Non-zero if differences found. */
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bic has_nul, tmp1, tmp2 /* Non-zero if NUL terminator. */
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orr syndrome, diff, has_nul
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cbz syndrome, L(loop_aligned)
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/* End of performance-critical section -- one 64B cache line. */
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L(end):
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#ifndef __AARCH64EB__
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rev syndrome, syndrome
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rev data1, data1
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/* The MS-non-zero bit of the syndrome marks either the first bit
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that is different, or the top bit of the first zero byte.
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Shifting left now will bring the critical information into the
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top bits. */
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clz pos, syndrome
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rev data2, data2
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lsl data1, data1, pos
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lsl data2, data2, pos
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/* But we need to zero-extend (char is unsigned) the value and then
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perform a signed 32-bit subtraction. */
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lsr data1, data1, #56
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sub result, data1, data2, lsr #56
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ret
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#else
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/* For big-endian we cannot use the trick with the syndrome value
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as carry-propagation can corrupt the upper bits if the trailing
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bytes in the string contain 0x01. */
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/* However, if there is no NUL byte in the dword, we can generate
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the result directly. We can't just subtract the bytes as the
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MSB might be significant. */
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cbnz has_nul, 1f
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cmp data1, data2
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cset result, ne
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cneg result, result, lo
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ret
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1:
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/* Re-compute the NUL-byte detection, using a byte-reversed value. */
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rev tmp3, data1
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sub tmp1, tmp3, zeroones
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orr tmp2, tmp3, #REP8_7f
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bic has_nul, tmp1, tmp2
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rev has_nul, has_nul
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orr syndrome, diff, has_nul
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clz pos, syndrome
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/* The MS-non-zero bit of the syndrome marks either the first bit
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that is different, or the top bit of the first zero byte.
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Shifting left now will bring the critical information into the
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top bits. */
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lsl data1, data1, pos
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lsl data2, data2, pos
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/* But we need to zero-extend (char is unsigned) the value and then
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perform a signed 32-bit subtraction. */
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lsr data1, data1, #56
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sub result, data1, data2, lsr #56
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ret
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#endif
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L(mutual_align):
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/* Sources are mutually aligned, but are not currently at an
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alignment boundary. Round down the addresses and then mask off
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the bytes that preceed the start point. */
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bic src1, src1, #7
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bic src2, src2, #7
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lsl tmp1, tmp1, #3 /* Bytes beyond alignment -> bits. */
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ldr data1, [src1], #8
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neg tmp1, tmp1 /* Bits to alignment -64. */
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ldr data2, [src2], #8
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mov tmp2, #~0
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#ifdef __AARCH64EB__
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/* Big-endian. Early bytes are at MSB. */
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lsl tmp2, tmp2, tmp1 /* Shift (tmp1 & 63). */
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#else
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/* Little-endian. Early bytes are at LSB. */
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lsr tmp2, tmp2, tmp1 /* Shift (tmp1 & 63). */
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#endif
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orr data1, data1, tmp2
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orr data2, data2, tmp2
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b L(start_realigned)
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L(misaligned8):
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/* Align SRC1 to 8 bytes and then compare 8 bytes at a time, always
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checking to make sure that we don't access beyond page boundary in
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SRC2. */
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tst src1, #7
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b.eq L(loop_misaligned)
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L(do_misaligned):
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ldrb data1w, [src1], #1
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ldrb data2w, [src2], #1
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cmp data1w, #1
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ccmp data1w, data2w, #0, cs /* NZCV = 0b0000. */
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b.ne L(done)
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tst src1, #7
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b.ne L(do_misaligned)
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L(loop_misaligned):
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/* Test if we are within the last dword of the end of a 4K page. If
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yes then jump back to the misaligned loop to copy a byte at a time. */
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and tmp1, src2, #0xff8
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eor tmp1, tmp1, #0xff8
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cbz tmp1, L(do_misaligned)
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ldr data1, [src1], #8
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ldr data2, [src2], #8
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sub tmp1, data1, zeroones
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orr tmp2, data1, #REP8_7f
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eor diff, data1, data2 /* Non-zero if differences found. */
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bic has_nul, tmp1, tmp2 /* Non-zero if NUL terminator. */
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orr syndrome, diff, has_nul
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cbz syndrome, L(loop_misaligned)
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b L(end)
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L(done):
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sub result, data1, data2
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ret
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SYM_FUNC_END_PI(strcmp)
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EXPORT_SYMBOL_NOHWKASAN(strcmp)
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