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a7a7ee6f5a
Terminate vdesc when terminating an ongoing transfer.
This will ensure that the vdesc is present in the desc_terminated list
The descriptor will be freed later in desc_free_list().
This fixes the memory leaks which can happen when terminating an
ongoing transfer.
Fixes: ee17028009
("dmaengine: tegra: Add tegra gpcdma driver")
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Link: https://lore.kernel.org/r/20230118115801.15210-1-akhilrajeev@nvidia.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
1545 lines
43 KiB
C
1545 lines
43 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* DMA driver for NVIDIA Tegra GPC DMA controller.
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*
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* Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/bitfield.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/iommu.h>
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#include <linux/iopoll.h>
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#include <linux/minmax.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_dma.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#include <dt-bindings/memory/tegra186-mc.h>
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#include "virt-dma.h"
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/* CSR register */
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#define TEGRA_GPCDMA_CHAN_CSR 0x00
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#define TEGRA_GPCDMA_CSR_ENB BIT(31)
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#define TEGRA_GPCDMA_CSR_IE_EOC BIT(30)
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#define TEGRA_GPCDMA_CSR_ONCE BIT(27)
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#define TEGRA_GPCDMA_CSR_FC_MODE GENMASK(25, 24)
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#define TEGRA_GPCDMA_CSR_FC_MODE_NO_MMIO \
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FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 0)
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#define TEGRA_GPCDMA_CSR_FC_MODE_ONE_MMIO \
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FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 1)
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#define TEGRA_GPCDMA_CSR_FC_MODE_TWO_MMIO \
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FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 2)
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#define TEGRA_GPCDMA_CSR_FC_MODE_FOUR_MMIO \
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FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 3)
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#define TEGRA_GPCDMA_CSR_DMA GENMASK(23, 21)
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#define TEGRA_GPCDMA_CSR_DMA_IO2MEM_NO_FC \
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FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 0)
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#define TEGRA_GPCDMA_CSR_DMA_IO2MEM_FC \
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FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 1)
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#define TEGRA_GPCDMA_CSR_DMA_MEM2IO_NO_FC \
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FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 2)
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#define TEGRA_GPCDMA_CSR_DMA_MEM2IO_FC \
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FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 3)
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#define TEGRA_GPCDMA_CSR_DMA_MEM2MEM \
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FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 4)
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#define TEGRA_GPCDMA_CSR_DMA_FIXED_PAT \
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FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 6)
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#define TEGRA_GPCDMA_CSR_REQ_SEL_MASK GENMASK(20, 16)
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#define TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED \
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FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, 4)
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#define TEGRA_GPCDMA_CSR_IRQ_MASK BIT(15)
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#define TEGRA_GPCDMA_CSR_WEIGHT GENMASK(13, 10)
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/* STATUS register */
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#define TEGRA_GPCDMA_CHAN_STATUS 0x004
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#define TEGRA_GPCDMA_STATUS_BUSY BIT(31)
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#define TEGRA_GPCDMA_STATUS_ISE_EOC BIT(30)
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#define TEGRA_GPCDMA_STATUS_PING_PONG BIT(28)
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#define TEGRA_GPCDMA_STATUS_DMA_ACTIVITY BIT(27)
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#define TEGRA_GPCDMA_STATUS_CHANNEL_PAUSE BIT(26)
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#define TEGRA_GPCDMA_STATUS_CHANNEL_RX BIT(25)
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#define TEGRA_GPCDMA_STATUS_CHANNEL_TX BIT(24)
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#define TEGRA_GPCDMA_STATUS_IRQ_INTR_STA BIT(23)
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#define TEGRA_GPCDMA_STATUS_IRQ_STA BIT(21)
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#define TEGRA_GPCDMA_STATUS_IRQ_TRIG_STA BIT(20)
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#define TEGRA_GPCDMA_CHAN_CSRE 0x008
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#define TEGRA_GPCDMA_CHAN_CSRE_PAUSE BIT(31)
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/* Source address */
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#define TEGRA_GPCDMA_CHAN_SRC_PTR 0x00C
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/* Destination address */
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#define TEGRA_GPCDMA_CHAN_DST_PTR 0x010
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/* High address pointer */
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#define TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR 0x014
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#define TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR GENMASK(7, 0)
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#define TEGRA_GPCDMA_HIGH_ADDR_DST_PTR GENMASK(23, 16)
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/* MC sequence register */
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#define TEGRA_GPCDMA_CHAN_MCSEQ 0x18
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#define TEGRA_GPCDMA_MCSEQ_DATA_SWAP BIT(31)
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#define TEGRA_GPCDMA_MCSEQ_REQ_COUNT GENMASK(30, 25)
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#define TEGRA_GPCDMA_MCSEQ_BURST GENMASK(24, 23)
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#define TEGRA_GPCDMA_MCSEQ_BURST_2 \
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FIELD_PREP(TEGRA_GPCDMA_MCSEQ_BURST, 0)
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#define TEGRA_GPCDMA_MCSEQ_BURST_16 \
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FIELD_PREP(TEGRA_GPCDMA_MCSEQ_BURST, 3)
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#define TEGRA_GPCDMA_MCSEQ_WRAP1 GENMASK(22, 20)
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#define TEGRA_GPCDMA_MCSEQ_WRAP0 GENMASK(19, 17)
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#define TEGRA_GPCDMA_MCSEQ_WRAP_NONE 0
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#define TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK GENMASK(13, 7)
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#define TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK GENMASK(6, 0)
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/* MMIO sequence register */
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#define TEGRA_GPCDMA_CHAN_MMIOSEQ 0x01c
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#define TEGRA_GPCDMA_MMIOSEQ_DBL_BUF BIT(31)
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#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH GENMASK(30, 28)
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#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_8 \
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FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH, 0)
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#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_16 \
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FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH, 1)
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#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_32 \
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FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH, 2)
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#define TEGRA_GPCDMA_MMIOSEQ_DATA_SWAP BIT(27)
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#define TEGRA_GPCDMA_MMIOSEQ_BURST_SHIFT 23
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#define TEGRA_GPCDMA_MMIOSEQ_BURST_MIN 2U
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#define TEGRA_GPCDMA_MMIOSEQ_BURST_MAX 32U
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#define TEGRA_GPCDMA_MMIOSEQ_BURST(bs) \
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(GENMASK((fls(bs) - 2), 0) << TEGRA_GPCDMA_MMIOSEQ_BURST_SHIFT)
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#define TEGRA_GPCDMA_MMIOSEQ_MASTER_ID GENMASK(22, 19)
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#define TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD GENMASK(18, 16)
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#define TEGRA_GPCDMA_MMIOSEQ_MMIO_PROT GENMASK(8, 7)
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/* Channel WCOUNT */
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#define TEGRA_GPCDMA_CHAN_WCOUNT 0x20
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/* Transfer count */
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#define TEGRA_GPCDMA_CHAN_XFER_COUNT 0x24
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/* DMA byte count status */
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#define TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS 0x28
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/* Error Status Register */
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#define TEGRA_GPCDMA_CHAN_ERR_STATUS 0x30
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#define TEGRA_GPCDMA_CHAN_ERR_TYPE_SHIFT 8
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#define TEGRA_GPCDMA_CHAN_ERR_TYPE_MASK 0xF
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#define TEGRA_GPCDMA_CHAN_ERR_TYPE(err) ( \
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((err) >> TEGRA_GPCDMA_CHAN_ERR_TYPE_SHIFT) & \
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TEGRA_GPCDMA_CHAN_ERR_TYPE_MASK)
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#define TEGRA_DMA_BM_FIFO_FULL_ERR 0xF
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#define TEGRA_DMA_PERIPH_FIFO_FULL_ERR 0xE
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#define TEGRA_DMA_PERIPH_ID_ERR 0xD
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#define TEGRA_DMA_STREAM_ID_ERR 0xC
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#define TEGRA_DMA_MC_SLAVE_ERR 0xB
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#define TEGRA_DMA_MMIO_SLAVE_ERR 0xA
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/* Fixed Pattern */
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#define TEGRA_GPCDMA_CHAN_FIXED_PATTERN 0x34
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#define TEGRA_GPCDMA_CHAN_TZ 0x38
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#define TEGRA_GPCDMA_CHAN_TZ_MMIO_PROT_1 BIT(0)
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#define TEGRA_GPCDMA_CHAN_TZ_MC_PROT_1 BIT(1)
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#define TEGRA_GPCDMA_CHAN_SPARE 0x3c
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#define TEGRA_GPCDMA_CHAN_SPARE_EN_LEGACY_FC BIT(16)
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/*
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* If any burst is in flight and DMA paused then this is the time to complete
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* on-flight burst and update DMA status register.
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*/
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#define TEGRA_GPCDMA_BURST_COMPLETE_TIME 10
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#define TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT 5000 /* 5 msec */
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/* Channel base address offset from GPCDMA base address */
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#define TEGRA_GPCDMA_CHANNEL_BASE_ADDR_OFFSET 0x10000
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/* Default channel mask reserving channel0 */
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#define TEGRA_GPCDMA_DEFAULT_CHANNEL_MASK 0xfffffffe
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struct tegra_dma;
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struct tegra_dma_channel;
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/*
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* tegra_dma_chip_data Tegra chip specific DMA data
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* @nr_channels: Number of channels available in the controller.
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* @channel_reg_size: Channel register size.
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* @max_dma_count: Maximum DMA transfer count supported by DMA controller.
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* @hw_support_pause: DMA HW engine support pause of the channel.
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*/
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struct tegra_dma_chip_data {
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bool hw_support_pause;
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unsigned int nr_channels;
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unsigned int channel_reg_size;
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unsigned int max_dma_count;
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int (*terminate)(struct tegra_dma_channel *tdc);
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};
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/* DMA channel registers */
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struct tegra_dma_channel_regs {
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u32 csr;
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u32 src_ptr;
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u32 dst_ptr;
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u32 high_addr_ptr;
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u32 mc_seq;
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u32 mmio_seq;
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u32 wcount;
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u32 fixed_pattern;
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};
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/*
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* tegra_dma_sg_req: DMA request details to configure hardware. This
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* contains the details for one transfer to configure DMA hw.
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* The client's request for data transfer can be broken into multiple
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* sub-transfer as per requester details and hw support. This sub transfer
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* get added as an array in Tegra DMA desc which manages the transfer details.
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*/
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struct tegra_dma_sg_req {
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unsigned int len;
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struct tegra_dma_channel_regs ch_regs;
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};
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/*
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* tegra_dma_desc: Tegra DMA descriptors which uses virt_dma_desc to
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* manage client request and keep track of transfer status, callbacks
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* and request counts etc.
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*/
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struct tegra_dma_desc {
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bool cyclic;
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unsigned int bytes_req;
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unsigned int bytes_xfer;
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unsigned int sg_idx;
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unsigned int sg_count;
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struct virt_dma_desc vd;
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struct tegra_dma_channel *tdc;
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struct tegra_dma_sg_req sg_req[];
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};
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/*
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* tegra_dma_channel: Channel specific information
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*/
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struct tegra_dma_channel {
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bool config_init;
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char name[30];
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enum dma_transfer_direction sid_dir;
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int id;
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int irq;
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int slave_id;
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struct tegra_dma *tdma;
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struct virt_dma_chan vc;
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struct tegra_dma_desc *dma_desc;
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struct dma_slave_config dma_sconfig;
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unsigned int stream_id;
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unsigned long chan_base_offset;
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};
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/*
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* tegra_dma: Tegra DMA specific information
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*/
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struct tegra_dma {
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const struct tegra_dma_chip_data *chip_data;
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unsigned long sid_m2d_reserved;
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unsigned long sid_d2m_reserved;
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u32 chan_mask;
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void __iomem *base_addr;
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struct device *dev;
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struct dma_device dma_dev;
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struct reset_control *rst;
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struct tegra_dma_channel channels[];
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};
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static inline void tdc_write(struct tegra_dma_channel *tdc,
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u32 reg, u32 val)
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{
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writel_relaxed(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg);
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}
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static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
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{
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return readl_relaxed(tdc->tdma->base_addr + tdc->chan_base_offset + reg);
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}
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static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
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{
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return container_of(dc, struct tegra_dma_channel, vc.chan);
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}
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static inline struct tegra_dma_desc *vd_to_tegra_dma_desc(struct virt_dma_desc *vd)
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{
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return container_of(vd, struct tegra_dma_desc, vd);
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}
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static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
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{
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return tdc->vc.chan.device->dev;
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}
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static void tegra_dma_dump_chan_regs(struct tegra_dma_channel *tdc)
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{
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dev_dbg(tdc2dev(tdc), "DMA Channel %d name %s register dump:\n",
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tdc->id, tdc->name);
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dev_dbg(tdc2dev(tdc), "CSR %x STA %x CSRE %x SRC %x DST %x\n",
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tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR),
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tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS),
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tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE),
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tdc_read(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR),
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tdc_read(tdc, TEGRA_GPCDMA_CHAN_DST_PTR)
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);
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dev_dbg(tdc2dev(tdc), "MCSEQ %x IOSEQ %x WCNT %x XFER %x BSTA %x\n",
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tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ),
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tdc_read(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ),
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tdc_read(tdc, TEGRA_GPCDMA_CHAN_WCOUNT),
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tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT),
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tdc_read(tdc, TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS)
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);
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dev_dbg(tdc2dev(tdc), "DMA ERR_STA %x\n",
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tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS));
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}
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static int tegra_dma_sid_reserve(struct tegra_dma_channel *tdc,
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enum dma_transfer_direction direction)
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{
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struct tegra_dma *tdma = tdc->tdma;
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int sid = tdc->slave_id;
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if (!is_slave_direction(direction))
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return 0;
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switch (direction) {
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case DMA_MEM_TO_DEV:
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if (test_and_set_bit(sid, &tdma->sid_m2d_reserved)) {
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dev_err(tdma->dev, "slave id already in use\n");
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return -EINVAL;
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}
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break;
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case DMA_DEV_TO_MEM:
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if (test_and_set_bit(sid, &tdma->sid_d2m_reserved)) {
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dev_err(tdma->dev, "slave id already in use\n");
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return -EINVAL;
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}
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break;
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default:
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break;
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}
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tdc->sid_dir = direction;
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return 0;
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}
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static void tegra_dma_sid_free(struct tegra_dma_channel *tdc)
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{
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struct tegra_dma *tdma = tdc->tdma;
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int sid = tdc->slave_id;
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switch (tdc->sid_dir) {
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case DMA_MEM_TO_DEV:
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clear_bit(sid, &tdma->sid_m2d_reserved);
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break;
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case DMA_DEV_TO_MEM:
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clear_bit(sid, &tdma->sid_d2m_reserved);
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break;
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default:
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break;
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}
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tdc->sid_dir = DMA_TRANS_NONE;
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}
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static void tegra_dma_desc_free(struct virt_dma_desc *vd)
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{
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kfree(container_of(vd, struct tegra_dma_desc, vd));
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}
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static int tegra_dma_slave_config(struct dma_chan *dc,
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struct dma_slave_config *sconfig)
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{
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struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
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memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
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tdc->config_init = true;
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return 0;
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}
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static int tegra_dma_pause(struct tegra_dma_channel *tdc)
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{
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int ret;
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u32 val;
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val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE);
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val |= TEGRA_GPCDMA_CHAN_CSRE_PAUSE;
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tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val);
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/* Wait until busy bit is de-asserted */
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ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +
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tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS,
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val,
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!(val & TEGRA_GPCDMA_STATUS_BUSY),
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TEGRA_GPCDMA_BURST_COMPLETE_TIME,
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TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT);
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if (ret) {
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dev_err(tdc2dev(tdc), "DMA pause timed out\n");
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tegra_dma_dump_chan_regs(tdc);
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}
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return ret;
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}
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static int tegra_dma_device_pause(struct dma_chan *dc)
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{
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struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
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unsigned long flags;
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int ret;
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if (!tdc->tdma->chip_data->hw_support_pause)
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return -ENOSYS;
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spin_lock_irqsave(&tdc->vc.lock, flags);
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ret = tegra_dma_pause(tdc);
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spin_unlock_irqrestore(&tdc->vc.lock, flags);
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return ret;
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}
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static void tegra_dma_resume(struct tegra_dma_channel *tdc)
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{
|
|
u32 val;
|
|
|
|
val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE);
|
|
val &= ~TEGRA_GPCDMA_CHAN_CSRE_PAUSE;
|
|
tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val);
|
|
}
|
|
|
|
static int tegra_dma_device_resume(struct dma_chan *dc)
|
|
{
|
|
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
|
|
unsigned long flags;
|
|
|
|
if (!tdc->tdma->chip_data->hw_support_pause)
|
|
return -ENOSYS;
|
|
|
|
spin_lock_irqsave(&tdc->vc.lock, flags);
|
|
tegra_dma_resume(tdc);
|
|
spin_unlock_irqrestore(&tdc->vc.lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline int tegra_dma_pause_noerr(struct tegra_dma_channel *tdc)
|
|
{
|
|
/* Return 0 irrespective of PAUSE status.
|
|
* This is useful to recover channels that can exit out of flush
|
|
* state when the channel is disabled.
|
|
*/
|
|
|
|
tegra_dma_pause(tdc);
|
|
return 0;
|
|
}
|
|
|
|
static void tegra_dma_disable(struct tegra_dma_channel *tdc)
|
|
{
|
|
u32 csr, status;
|
|
|
|
csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);
|
|
|
|
/* Disable interrupts */
|
|
csr &= ~TEGRA_GPCDMA_CSR_IE_EOC;
|
|
|
|
/* Disable DMA */
|
|
csr &= ~TEGRA_GPCDMA_CSR_ENB;
|
|
tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr);
|
|
|
|
/* Clear interrupt status if it is there */
|
|
status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
|
|
if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) {
|
|
dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
|
|
tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS, status);
|
|
}
|
|
}
|
|
|
|
static void tegra_dma_configure_next_sg(struct tegra_dma_channel *tdc)
|
|
{
|
|
struct tegra_dma_desc *dma_desc = tdc->dma_desc;
|
|
struct tegra_dma_channel_regs *ch_regs;
|
|
int ret;
|
|
u32 val;
|
|
|
|
dma_desc->sg_idx++;
|
|
|
|
/* Reset the sg index for cyclic transfers */
|
|
if (dma_desc->sg_idx == dma_desc->sg_count)
|
|
dma_desc->sg_idx = 0;
|
|
|
|
/* Configure next transfer immediately after DMA is busy */
|
|
ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +
|
|
tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS,
|
|
val,
|
|
(val & TEGRA_GPCDMA_STATUS_BUSY), 0,
|
|
TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT);
|
|
if (ret)
|
|
return;
|
|
|
|
ch_regs = &dma_desc->sg_req[dma_desc->sg_idx].ch_regs;
|
|
|
|
tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount);
|
|
tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr);
|
|
tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr);
|
|
tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr);
|
|
|
|
/* Start DMA */
|
|
tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR,
|
|
ch_regs->csr | TEGRA_GPCDMA_CSR_ENB);
|
|
}
|
|
|
|
static void tegra_dma_start(struct tegra_dma_channel *tdc)
|
|
{
|
|
struct tegra_dma_desc *dma_desc = tdc->dma_desc;
|
|
struct tegra_dma_channel_regs *ch_regs;
|
|
struct virt_dma_desc *vdesc;
|
|
|
|
if (!dma_desc) {
|
|
vdesc = vchan_next_desc(&tdc->vc);
|
|
if (!vdesc)
|
|
return;
|
|
|
|
dma_desc = vd_to_tegra_dma_desc(vdesc);
|
|
list_del(&vdesc->node);
|
|
dma_desc->tdc = tdc;
|
|
tdc->dma_desc = dma_desc;
|
|
|
|
tegra_dma_resume(tdc);
|
|
}
|
|
|
|
ch_regs = &dma_desc->sg_req[dma_desc->sg_idx].ch_regs;
|
|
|
|
tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount);
|
|
tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, 0);
|
|
tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr);
|
|
tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr);
|
|
tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr);
|
|
tdc_write(tdc, TEGRA_GPCDMA_CHAN_FIXED_PATTERN, ch_regs->fixed_pattern);
|
|
tdc_write(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ, ch_regs->mmio_seq);
|
|
tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, ch_regs->mc_seq);
|
|
tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, ch_regs->csr);
|
|
|
|
/* Start DMA */
|
|
tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR,
|
|
ch_regs->csr | TEGRA_GPCDMA_CSR_ENB);
|
|
}
|
|
|
|
static void tegra_dma_xfer_complete(struct tegra_dma_channel *tdc)
|
|
{
|
|
vchan_cookie_complete(&tdc->dma_desc->vd);
|
|
|
|
tegra_dma_sid_free(tdc);
|
|
tdc->dma_desc = NULL;
|
|
}
|
|
|
|
static void tegra_dma_chan_decode_error(struct tegra_dma_channel *tdc,
|
|
unsigned int err_status)
|
|
{
|
|
switch (TEGRA_GPCDMA_CHAN_ERR_TYPE(err_status)) {
|
|
case TEGRA_DMA_BM_FIFO_FULL_ERR:
|
|
dev_err(tdc->tdma->dev,
|
|
"GPCDMA CH%d bm fifo full\n", tdc->id);
|
|
break;
|
|
|
|
case TEGRA_DMA_PERIPH_FIFO_FULL_ERR:
|
|
dev_err(tdc->tdma->dev,
|
|
"GPCDMA CH%d peripheral fifo full\n", tdc->id);
|
|
break;
|
|
|
|
case TEGRA_DMA_PERIPH_ID_ERR:
|
|
dev_err(tdc->tdma->dev,
|
|
"GPCDMA CH%d illegal peripheral id\n", tdc->id);
|
|
break;
|
|
|
|
case TEGRA_DMA_STREAM_ID_ERR:
|
|
dev_err(tdc->tdma->dev,
|
|
"GPCDMA CH%d illegal stream id\n", tdc->id);
|
|
break;
|
|
|
|
case TEGRA_DMA_MC_SLAVE_ERR:
|
|
dev_err(tdc->tdma->dev,
|
|
"GPCDMA CH%d mc slave error\n", tdc->id);
|
|
break;
|
|
|
|
case TEGRA_DMA_MMIO_SLAVE_ERR:
|
|
dev_err(tdc->tdma->dev,
|
|
"GPCDMA CH%d mmio slave error\n", tdc->id);
|
|
break;
|
|
|
|
default:
|
|
dev_err(tdc->tdma->dev,
|
|
"GPCDMA CH%d security violation %x\n", tdc->id,
|
|
err_status);
|
|
}
|
|
}
|
|
|
|
static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
|
|
{
|
|
struct tegra_dma_channel *tdc = dev_id;
|
|
struct tegra_dma_desc *dma_desc = tdc->dma_desc;
|
|
struct tegra_dma_sg_req *sg_req;
|
|
u32 status;
|
|
|
|
/* Check channel error status register */
|
|
status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS);
|
|
if (status) {
|
|
tegra_dma_chan_decode_error(tdc, status);
|
|
tegra_dma_dump_chan_regs(tdc);
|
|
tdc_write(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS, 0xFFFFFFFF);
|
|
}
|
|
|
|
spin_lock(&tdc->vc.lock);
|
|
status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
|
|
if (!(status & TEGRA_GPCDMA_STATUS_ISE_EOC))
|
|
goto irq_done;
|
|
|
|
tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS,
|
|
TEGRA_GPCDMA_STATUS_ISE_EOC);
|
|
|
|
if (!dma_desc)
|
|
goto irq_done;
|
|
|
|
sg_req = dma_desc->sg_req;
|
|
dma_desc->bytes_xfer += sg_req[dma_desc->sg_idx].len;
|
|
|
|
if (dma_desc->cyclic) {
|
|
vchan_cyclic_callback(&dma_desc->vd);
|
|
tegra_dma_configure_next_sg(tdc);
|
|
} else {
|
|
dma_desc->sg_idx++;
|
|
if (dma_desc->sg_idx == dma_desc->sg_count)
|
|
tegra_dma_xfer_complete(tdc);
|
|
else
|
|
tegra_dma_start(tdc);
|
|
}
|
|
|
|
irq_done:
|
|
spin_unlock(&tdc->vc.lock);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static void tegra_dma_issue_pending(struct dma_chan *dc)
|
|
{
|
|
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
|
|
unsigned long flags;
|
|
|
|
if (tdc->dma_desc)
|
|
return;
|
|
|
|
spin_lock_irqsave(&tdc->vc.lock, flags);
|
|
if (vchan_issue_pending(&tdc->vc))
|
|
tegra_dma_start(tdc);
|
|
|
|
/*
|
|
* For cyclic DMA transfers, program the second
|
|
* transfer parameters as soon as the first DMA
|
|
* transfer is started inorder for the DMA
|
|
* controller to trigger the second transfer
|
|
* with the correct parameters.
|
|
*/
|
|
if (tdc->dma_desc && tdc->dma_desc->cyclic)
|
|
tegra_dma_configure_next_sg(tdc);
|
|
|
|
spin_unlock_irqrestore(&tdc->vc.lock, flags);
|
|
}
|
|
|
|
static int tegra_dma_stop_client(struct tegra_dma_channel *tdc)
|
|
{
|
|
int ret;
|
|
u32 status, csr;
|
|
|
|
/*
|
|
* Change the client associated with the DMA channel
|
|
* to stop DMA engine from starting any more bursts for
|
|
* the given client and wait for in flight bursts to complete
|
|
*/
|
|
csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);
|
|
csr &= ~(TEGRA_GPCDMA_CSR_REQ_SEL_MASK);
|
|
csr |= TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED;
|
|
tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr);
|
|
|
|
/* Wait for in flight data transfer to finish */
|
|
udelay(TEGRA_GPCDMA_BURST_COMPLETE_TIME);
|
|
|
|
/* If TX/RX path is still active wait till it becomes
|
|
* inactive
|
|
*/
|
|
|
|
ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +
|
|
tdc->chan_base_offset +
|
|
TEGRA_GPCDMA_CHAN_STATUS,
|
|
status,
|
|
!(status & (TEGRA_GPCDMA_STATUS_CHANNEL_TX |
|
|
TEGRA_GPCDMA_STATUS_CHANNEL_RX)),
|
|
5,
|
|
TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT);
|
|
if (ret) {
|
|
dev_err(tdc2dev(tdc), "Timeout waiting for DMA burst completion!\n");
|
|
tegra_dma_dump_chan_regs(tdc);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int tegra_dma_terminate_all(struct dma_chan *dc)
|
|
{
|
|
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
|
|
unsigned long flags;
|
|
LIST_HEAD(head);
|
|
int err;
|
|
|
|
spin_lock_irqsave(&tdc->vc.lock, flags);
|
|
|
|
if (tdc->dma_desc) {
|
|
err = tdc->tdma->chip_data->terminate(tdc);
|
|
if (err) {
|
|
spin_unlock_irqrestore(&tdc->vc.lock, flags);
|
|
return err;
|
|
}
|
|
|
|
vchan_terminate_vdesc(&tdc->dma_desc->vd);
|
|
tegra_dma_disable(tdc);
|
|
tdc->dma_desc = NULL;
|
|
}
|
|
|
|
tegra_dma_sid_free(tdc);
|
|
vchan_get_all_descriptors(&tdc->vc, &head);
|
|
spin_unlock_irqrestore(&tdc->vc.lock, flags);
|
|
|
|
vchan_dma_desc_free_list(&tdc->vc, &head);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_dma_get_residual(struct tegra_dma_channel *tdc)
|
|
{
|
|
struct tegra_dma_desc *dma_desc = tdc->dma_desc;
|
|
struct tegra_dma_sg_req *sg_req = dma_desc->sg_req;
|
|
unsigned int bytes_xfer, residual;
|
|
u32 wcount = 0, status;
|
|
|
|
wcount = tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT);
|
|
|
|
/*
|
|
* Set wcount = 0 if EOC bit is set. The transfer would have
|
|
* already completed and the CHAN_XFER_COUNT could have updated
|
|
* for the next transfer, specifically in case of cyclic transfers.
|
|
*/
|
|
status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
|
|
if (status & TEGRA_GPCDMA_STATUS_ISE_EOC)
|
|
wcount = 0;
|
|
|
|
bytes_xfer = dma_desc->bytes_xfer +
|
|
sg_req[dma_desc->sg_idx].len - (wcount * 4);
|
|
|
|
residual = dma_desc->bytes_req - (bytes_xfer % dma_desc->bytes_req);
|
|
|
|
return residual;
|
|
}
|
|
|
|
static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
|
|
dma_cookie_t cookie,
|
|
struct dma_tx_state *txstate)
|
|
{
|
|
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
|
|
struct tegra_dma_desc *dma_desc;
|
|
struct virt_dma_desc *vd;
|
|
unsigned int residual;
|
|
unsigned long flags;
|
|
enum dma_status ret;
|
|
|
|
ret = dma_cookie_status(dc, cookie, txstate);
|
|
if (ret == DMA_COMPLETE)
|
|
return ret;
|
|
|
|
spin_lock_irqsave(&tdc->vc.lock, flags);
|
|
vd = vchan_find_desc(&tdc->vc, cookie);
|
|
if (vd) {
|
|
dma_desc = vd_to_tegra_dma_desc(vd);
|
|
residual = dma_desc->bytes_req;
|
|
dma_set_residue(txstate, residual);
|
|
} else if (tdc->dma_desc && tdc->dma_desc->vd.tx.cookie == cookie) {
|
|
residual = tegra_dma_get_residual(tdc);
|
|
dma_set_residue(txstate, residual);
|
|
} else {
|
|
dev_err(tdc2dev(tdc), "cookie %d is not found\n", cookie);
|
|
}
|
|
spin_unlock_irqrestore(&tdc->vc.lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static inline int get_bus_width(struct tegra_dma_channel *tdc,
|
|
enum dma_slave_buswidth slave_bw)
|
|
{
|
|
switch (slave_bw) {
|
|
case DMA_SLAVE_BUSWIDTH_1_BYTE:
|
|
return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_8;
|
|
case DMA_SLAVE_BUSWIDTH_2_BYTES:
|
|
return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_16;
|
|
case DMA_SLAVE_BUSWIDTH_4_BYTES:
|
|
return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_32;
|
|
default:
|
|
dev_err(tdc2dev(tdc), "given slave bus width is not supported\n");
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
static unsigned int get_burst_size(struct tegra_dma_channel *tdc,
|
|
u32 burst_size, enum dma_slave_buswidth slave_bw,
|
|
int len)
|
|
{
|
|
unsigned int burst_mmio_width, burst_byte;
|
|
|
|
/*
|
|
* burst_size from client is in terms of the bus_width.
|
|
* convert that into words.
|
|
* If burst_size is not specified from client, then use
|
|
* len to calculate the optimum burst size
|
|
*/
|
|
burst_byte = burst_size ? burst_size * slave_bw : len;
|
|
burst_mmio_width = burst_byte / 4;
|
|
|
|
if (burst_mmio_width < TEGRA_GPCDMA_MMIOSEQ_BURST_MIN)
|
|
return 0;
|
|
|
|
burst_mmio_width = min(burst_mmio_width, TEGRA_GPCDMA_MMIOSEQ_BURST_MAX);
|
|
|
|
return TEGRA_GPCDMA_MMIOSEQ_BURST(burst_mmio_width);
|
|
}
|
|
|
|
static int get_transfer_param(struct tegra_dma_channel *tdc,
|
|
enum dma_transfer_direction direction,
|
|
u32 *apb_addr,
|
|
u32 *mmio_seq,
|
|
u32 *csr,
|
|
unsigned int *burst_size,
|
|
enum dma_slave_buswidth *slave_bw)
|
|
{
|
|
switch (direction) {
|
|
case DMA_MEM_TO_DEV:
|
|
*apb_addr = tdc->dma_sconfig.dst_addr;
|
|
*mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
|
|
*burst_size = tdc->dma_sconfig.dst_maxburst;
|
|
*slave_bw = tdc->dma_sconfig.dst_addr_width;
|
|
*csr = TEGRA_GPCDMA_CSR_DMA_MEM2IO_FC;
|
|
return 0;
|
|
case DMA_DEV_TO_MEM:
|
|
*apb_addr = tdc->dma_sconfig.src_addr;
|
|
*mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
|
|
*burst_size = tdc->dma_sconfig.src_maxburst;
|
|
*slave_bw = tdc->dma_sconfig.src_addr_width;
|
|
*csr = TEGRA_GPCDMA_CSR_DMA_IO2MEM_FC;
|
|
return 0;
|
|
default:
|
|
dev_err(tdc2dev(tdc), "DMA direction is not supported\n");
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static struct dma_async_tx_descriptor *
|
|
tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_addr_t dest, int value,
|
|
size_t len, unsigned long flags)
|
|
{
|
|
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
|
|
unsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count;
|
|
struct tegra_dma_sg_req *sg_req;
|
|
struct tegra_dma_desc *dma_desc;
|
|
u32 csr, mc_seq;
|
|
|
|
if ((len & 3) || (dest & 3) || len > max_dma_count) {
|
|
dev_err(tdc2dev(tdc),
|
|
"DMA length/memory address is not supported\n");
|
|
return NULL;
|
|
}
|
|
|
|
/* Set DMA mode to fixed pattern */
|
|
csr = TEGRA_GPCDMA_CSR_DMA_FIXED_PAT;
|
|
/* Enable once or continuous mode */
|
|
csr |= TEGRA_GPCDMA_CSR_ONCE;
|
|
/* Enable IRQ mask */
|
|
csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
|
|
/* Enable the DMA interrupt */
|
|
if (flags & DMA_PREP_INTERRUPT)
|
|
csr |= TEGRA_GPCDMA_CSR_IE_EOC;
|
|
/* Configure default priority weight for the channel */
|
|
csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);
|
|
|
|
mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
|
|
/* retain stream-id and clean rest */
|
|
mc_seq &= TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK;
|
|
|
|
/* Set the address wrapping */
|
|
mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0,
|
|
TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
|
|
mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1,
|
|
TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
|
|
|
|
/* Program outstanding MC requests */
|
|
mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1);
|
|
/* Set burst size */
|
|
mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
|
|
|
|
dma_desc = kzalloc(struct_size(dma_desc, sg_req, 1), GFP_NOWAIT);
|
|
if (!dma_desc)
|
|
return NULL;
|
|
|
|
dma_desc->bytes_req = len;
|
|
dma_desc->sg_count = 1;
|
|
sg_req = dma_desc->sg_req;
|
|
|
|
sg_req[0].ch_regs.src_ptr = 0;
|
|
sg_req[0].ch_regs.dst_ptr = dest;
|
|
sg_req[0].ch_regs.high_addr_ptr =
|
|
FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
|
|
sg_req[0].ch_regs.fixed_pattern = value;
|
|
/* Word count reg takes value as (N +1) words */
|
|
sg_req[0].ch_regs.wcount = ((len - 4) >> 2);
|
|
sg_req[0].ch_regs.csr = csr;
|
|
sg_req[0].ch_regs.mmio_seq = 0;
|
|
sg_req[0].ch_regs.mc_seq = mc_seq;
|
|
sg_req[0].len = len;
|
|
|
|
dma_desc->cyclic = false;
|
|
return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
|
|
}
|
|
|
|
static struct dma_async_tx_descriptor *
|
|
tegra_dma_prep_dma_memcpy(struct dma_chan *dc, dma_addr_t dest,
|
|
dma_addr_t src, size_t len, unsigned long flags)
|
|
{
|
|
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
|
|
struct tegra_dma_sg_req *sg_req;
|
|
struct tegra_dma_desc *dma_desc;
|
|
unsigned int max_dma_count;
|
|
u32 csr, mc_seq;
|
|
|
|
max_dma_count = tdc->tdma->chip_data->max_dma_count;
|
|
if ((len & 3) || (src & 3) || (dest & 3) || len > max_dma_count) {
|
|
dev_err(tdc2dev(tdc),
|
|
"DMA length/memory address is not supported\n");
|
|
return NULL;
|
|
}
|
|
|
|
/* Set DMA mode to memory to memory transfer */
|
|
csr = TEGRA_GPCDMA_CSR_DMA_MEM2MEM;
|
|
/* Enable once or continuous mode */
|
|
csr |= TEGRA_GPCDMA_CSR_ONCE;
|
|
/* Enable IRQ mask */
|
|
csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
|
|
/* Enable the DMA interrupt */
|
|
if (flags & DMA_PREP_INTERRUPT)
|
|
csr |= TEGRA_GPCDMA_CSR_IE_EOC;
|
|
/* Configure default priority weight for the channel */
|
|
csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);
|
|
|
|
mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
|
|
/* retain stream-id and clean rest */
|
|
mc_seq &= (TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK) |
|
|
(TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK);
|
|
|
|
/* Set the address wrapping */
|
|
mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0,
|
|
TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
|
|
mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1,
|
|
TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
|
|
|
|
/* Program outstanding MC requests */
|
|
mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1);
|
|
/* Set burst size */
|
|
mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
|
|
|
|
dma_desc = kzalloc(struct_size(dma_desc, sg_req, 1), GFP_NOWAIT);
|
|
if (!dma_desc)
|
|
return NULL;
|
|
|
|
dma_desc->bytes_req = len;
|
|
dma_desc->sg_count = 1;
|
|
sg_req = dma_desc->sg_req;
|
|
|
|
sg_req[0].ch_regs.src_ptr = src;
|
|
sg_req[0].ch_regs.dst_ptr = dest;
|
|
sg_req[0].ch_regs.high_addr_ptr =
|
|
FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (src >> 32));
|
|
sg_req[0].ch_regs.high_addr_ptr |=
|
|
FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
|
|
/* Word count reg takes value as (N +1) words */
|
|
sg_req[0].ch_regs.wcount = ((len - 4) >> 2);
|
|
sg_req[0].ch_regs.csr = csr;
|
|
sg_req[0].ch_regs.mmio_seq = 0;
|
|
sg_req[0].ch_regs.mc_seq = mc_seq;
|
|
sg_req[0].len = len;
|
|
|
|
dma_desc->cyclic = false;
|
|
return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
|
|
}
|
|
|
|
static struct dma_async_tx_descriptor *
|
|
tegra_dma_prep_slave_sg(struct dma_chan *dc, struct scatterlist *sgl,
|
|
unsigned int sg_len, enum dma_transfer_direction direction,
|
|
unsigned long flags, void *context)
|
|
{
|
|
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
|
|
unsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count;
|
|
enum dma_slave_buswidth slave_bw = DMA_SLAVE_BUSWIDTH_UNDEFINED;
|
|
u32 csr, mc_seq, apb_ptr = 0, mmio_seq = 0;
|
|
struct tegra_dma_sg_req *sg_req;
|
|
struct tegra_dma_desc *dma_desc;
|
|
struct scatterlist *sg;
|
|
u32 burst_size;
|
|
unsigned int i;
|
|
int ret;
|
|
|
|
if (!tdc->config_init) {
|
|
dev_err(tdc2dev(tdc), "DMA channel is not configured\n");
|
|
return NULL;
|
|
}
|
|
if (sg_len < 1) {
|
|
dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
|
|
return NULL;
|
|
}
|
|
|
|
ret = tegra_dma_sid_reserve(tdc, direction);
|
|
if (ret)
|
|
return NULL;
|
|
|
|
ret = get_transfer_param(tdc, direction, &apb_ptr, &mmio_seq, &csr,
|
|
&burst_size, &slave_bw);
|
|
if (ret < 0)
|
|
return NULL;
|
|
|
|
/* Enable once or continuous mode */
|
|
csr |= TEGRA_GPCDMA_CSR_ONCE;
|
|
/* Program the slave id in requestor select */
|
|
csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, tdc->slave_id);
|
|
/* Enable IRQ mask */
|
|
csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
|
|
/* Configure default priority weight for the channel*/
|
|
csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);
|
|
|
|
/* Enable the DMA interrupt */
|
|
if (flags & DMA_PREP_INTERRUPT)
|
|
csr |= TEGRA_GPCDMA_CSR_IE_EOC;
|
|
|
|
mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
|
|
/* retain stream-id and clean rest */
|
|
mc_seq &= TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK;
|
|
|
|
/* Set the address wrapping on both MC and MMIO side */
|
|
|
|
mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0,
|
|
TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
|
|
mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1,
|
|
TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
|
|
mmio_seq |= FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD, 1);
|
|
|
|
/* Program 2 MC outstanding requests by default. */
|
|
mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1);
|
|
|
|
/* Setting MC burst size depending on MMIO burst size */
|
|
if (burst_size == 64)
|
|
mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
|
|
else
|
|
mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_2;
|
|
|
|
dma_desc = kzalloc(struct_size(dma_desc, sg_req, sg_len), GFP_NOWAIT);
|
|
if (!dma_desc)
|
|
return NULL;
|
|
|
|
dma_desc->sg_count = sg_len;
|
|
sg_req = dma_desc->sg_req;
|
|
|
|
/* Make transfer requests */
|
|
for_each_sg(sgl, sg, sg_len, i) {
|
|
u32 len;
|
|
dma_addr_t mem;
|
|
|
|
mem = sg_dma_address(sg);
|
|
len = sg_dma_len(sg);
|
|
|
|
if ((len & 3) || (mem & 3) || len > max_dma_count) {
|
|
dev_err(tdc2dev(tdc),
|
|
"DMA length/memory address is not supported\n");
|
|
kfree(dma_desc);
|
|
return NULL;
|
|
}
|
|
|
|
mmio_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
|
|
dma_desc->bytes_req += len;
|
|
|
|
if (direction == DMA_MEM_TO_DEV) {
|
|
sg_req[i].ch_regs.src_ptr = mem;
|
|
sg_req[i].ch_regs.dst_ptr = apb_ptr;
|
|
sg_req[i].ch_regs.high_addr_ptr =
|
|
FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32));
|
|
} else if (direction == DMA_DEV_TO_MEM) {
|
|
sg_req[i].ch_regs.src_ptr = apb_ptr;
|
|
sg_req[i].ch_regs.dst_ptr = mem;
|
|
sg_req[i].ch_regs.high_addr_ptr =
|
|
FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32));
|
|
}
|
|
|
|
/*
|
|
* Word count register takes input in words. Writing a value
|
|
* of N into word count register means a req of (N+1) words.
|
|
*/
|
|
sg_req[i].ch_regs.wcount = ((len - 4) >> 2);
|
|
sg_req[i].ch_regs.csr = csr;
|
|
sg_req[i].ch_regs.mmio_seq = mmio_seq;
|
|
sg_req[i].ch_regs.mc_seq = mc_seq;
|
|
sg_req[i].len = len;
|
|
}
|
|
|
|
dma_desc->cyclic = false;
|
|
return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
|
|
}
|
|
|
|
static struct dma_async_tx_descriptor *
|
|
tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
|
|
size_t period_len, enum dma_transfer_direction direction,
|
|
unsigned long flags)
|
|
{
|
|
enum dma_slave_buswidth slave_bw = DMA_SLAVE_BUSWIDTH_UNDEFINED;
|
|
u32 csr, mc_seq, apb_ptr = 0, mmio_seq = 0, burst_size;
|
|
unsigned int max_dma_count, len, period_count, i;
|
|
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
|
|
struct tegra_dma_desc *dma_desc;
|
|
struct tegra_dma_sg_req *sg_req;
|
|
dma_addr_t mem = buf_addr;
|
|
int ret;
|
|
|
|
if (!buf_len || !period_len) {
|
|
dev_err(tdc2dev(tdc), "Invalid buffer/period len\n");
|
|
return NULL;
|
|
}
|
|
|
|
if (!tdc->config_init) {
|
|
dev_err(tdc2dev(tdc), "DMA slave is not configured\n");
|
|
return NULL;
|
|
}
|
|
|
|
ret = tegra_dma_sid_reserve(tdc, direction);
|
|
if (ret)
|
|
return NULL;
|
|
|
|
/*
|
|
* We only support cycle transfer when buf_len is multiple of
|
|
* period_len.
|
|
*/
|
|
if (buf_len % period_len) {
|
|
dev_err(tdc2dev(tdc), "buf_len is not multiple of period_len\n");
|
|
return NULL;
|
|
}
|
|
|
|
len = period_len;
|
|
max_dma_count = tdc->tdma->chip_data->max_dma_count;
|
|
if ((len & 3) || (buf_addr & 3) || len > max_dma_count) {
|
|
dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n");
|
|
return NULL;
|
|
}
|
|
|
|
ret = get_transfer_param(tdc, direction, &apb_ptr, &mmio_seq, &csr,
|
|
&burst_size, &slave_bw);
|
|
if (ret < 0)
|
|
return NULL;
|
|
|
|
/* Enable once or continuous mode */
|
|
csr &= ~TEGRA_GPCDMA_CSR_ONCE;
|
|
/* Program the slave id in requestor select */
|
|
csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, tdc->slave_id);
|
|
/* Enable IRQ mask */
|
|
csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
|
|
/* Configure default priority weight for the channel*/
|
|
csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);
|
|
|
|
/* Enable the DMA interrupt */
|
|
if (flags & DMA_PREP_INTERRUPT)
|
|
csr |= TEGRA_GPCDMA_CSR_IE_EOC;
|
|
|
|
mmio_seq |= FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD, 1);
|
|
|
|
mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
|
|
/* retain stream-id and clean rest */
|
|
mc_seq &= TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK;
|
|
|
|
/* Set the address wrapping on both MC and MMIO side */
|
|
mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0,
|
|
TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
|
|
mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1,
|
|
TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
|
|
|
|
/* Program 2 MC outstanding requests by default. */
|
|
mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1);
|
|
/* Setting MC burst size depending on MMIO burst size */
|
|
if (burst_size == 64)
|
|
mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
|
|
else
|
|
mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_2;
|
|
|
|
period_count = buf_len / period_len;
|
|
dma_desc = kzalloc(struct_size(dma_desc, sg_req, period_count),
|
|
GFP_NOWAIT);
|
|
if (!dma_desc)
|
|
return NULL;
|
|
|
|
dma_desc->bytes_req = buf_len;
|
|
dma_desc->sg_count = period_count;
|
|
sg_req = dma_desc->sg_req;
|
|
|
|
/* Split transfer equal to period size */
|
|
for (i = 0; i < period_count; i++) {
|
|
mmio_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
|
|
if (direction == DMA_MEM_TO_DEV) {
|
|
sg_req[i].ch_regs.src_ptr = mem;
|
|
sg_req[i].ch_regs.dst_ptr = apb_ptr;
|
|
sg_req[i].ch_regs.high_addr_ptr =
|
|
FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32));
|
|
} else if (direction == DMA_DEV_TO_MEM) {
|
|
sg_req[i].ch_regs.src_ptr = apb_ptr;
|
|
sg_req[i].ch_regs.dst_ptr = mem;
|
|
sg_req[i].ch_regs.high_addr_ptr =
|
|
FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32));
|
|
}
|
|
/*
|
|
* Word count register takes input in words. Writing a value
|
|
* of N into word count register means a req of (N+1) words.
|
|
*/
|
|
sg_req[i].ch_regs.wcount = ((len - 4) >> 2);
|
|
sg_req[i].ch_regs.csr = csr;
|
|
sg_req[i].ch_regs.mmio_seq = mmio_seq;
|
|
sg_req[i].ch_regs.mc_seq = mc_seq;
|
|
sg_req[i].len = len;
|
|
|
|
mem += len;
|
|
}
|
|
|
|
dma_desc->cyclic = true;
|
|
|
|
return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
|
|
}
|
|
|
|
static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
|
|
{
|
|
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
|
|
int ret;
|
|
|
|
ret = request_irq(tdc->irq, tegra_dma_isr, 0, tdc->name, tdc);
|
|
if (ret) {
|
|
dev_err(tdc2dev(tdc), "request_irq failed for %s\n", tdc->name);
|
|
return ret;
|
|
}
|
|
|
|
dma_cookie_init(&tdc->vc.chan);
|
|
tdc->config_init = false;
|
|
return 0;
|
|
}
|
|
|
|
static void tegra_dma_chan_synchronize(struct dma_chan *dc)
|
|
{
|
|
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
|
|
|
|
synchronize_irq(tdc->irq);
|
|
vchan_synchronize(&tdc->vc);
|
|
}
|
|
|
|
static void tegra_dma_free_chan_resources(struct dma_chan *dc)
|
|
{
|
|
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
|
|
|
|
dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);
|
|
|
|
tegra_dma_terminate_all(dc);
|
|
synchronize_irq(tdc->irq);
|
|
|
|
tasklet_kill(&tdc->vc.task);
|
|
tdc->config_init = false;
|
|
tdc->slave_id = -1;
|
|
tdc->sid_dir = DMA_TRANS_NONE;
|
|
free_irq(tdc->irq, tdc);
|
|
|
|
vchan_free_chan_resources(&tdc->vc);
|
|
}
|
|
|
|
static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
|
|
struct of_dma *ofdma)
|
|
{
|
|
struct tegra_dma *tdma = ofdma->of_dma_data;
|
|
struct tegra_dma_channel *tdc;
|
|
struct dma_chan *chan;
|
|
|
|
chan = dma_get_any_slave_channel(&tdma->dma_dev);
|
|
if (!chan)
|
|
return NULL;
|
|
|
|
tdc = to_tegra_dma_chan(chan);
|
|
tdc->slave_id = dma_spec->args[0];
|
|
|
|
return chan;
|
|
}
|
|
|
|
static const struct tegra_dma_chip_data tegra186_dma_chip_data = {
|
|
.nr_channels = 32,
|
|
.channel_reg_size = SZ_64K,
|
|
.max_dma_count = SZ_1G,
|
|
.hw_support_pause = false,
|
|
.terminate = tegra_dma_stop_client,
|
|
};
|
|
|
|
static const struct tegra_dma_chip_data tegra194_dma_chip_data = {
|
|
.nr_channels = 32,
|
|
.channel_reg_size = SZ_64K,
|
|
.max_dma_count = SZ_1G,
|
|
.hw_support_pause = true,
|
|
.terminate = tegra_dma_pause,
|
|
};
|
|
|
|
static const struct tegra_dma_chip_data tegra234_dma_chip_data = {
|
|
.nr_channels = 32,
|
|
.channel_reg_size = SZ_64K,
|
|
.max_dma_count = SZ_1G,
|
|
.hw_support_pause = true,
|
|
.terminate = tegra_dma_pause_noerr,
|
|
};
|
|
|
|
static const struct of_device_id tegra_dma_of_match[] = {
|
|
{
|
|
.compatible = "nvidia,tegra186-gpcdma",
|
|
.data = &tegra186_dma_chip_data,
|
|
}, {
|
|
.compatible = "nvidia,tegra194-gpcdma",
|
|
.data = &tegra194_dma_chip_data,
|
|
}, {
|
|
.compatible = "nvidia,tegra234-gpcdma",
|
|
.data = &tegra234_dma_chip_data,
|
|
}, {
|
|
},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
|
|
|
|
static int tegra_dma_program_sid(struct tegra_dma_channel *tdc, int stream_id)
|
|
{
|
|
unsigned int reg_val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
|
|
|
|
reg_val &= ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK);
|
|
reg_val &= ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK);
|
|
|
|
reg_val |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK, stream_id);
|
|
reg_val |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK, stream_id);
|
|
|
|
tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, reg_val);
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_dma_probe(struct platform_device *pdev)
|
|
{
|
|
const struct tegra_dma_chip_data *cdata = NULL;
|
|
struct iommu_fwspec *iommu_spec;
|
|
unsigned int stream_id, i;
|
|
struct tegra_dma *tdma;
|
|
int ret;
|
|
|
|
cdata = of_device_get_match_data(&pdev->dev);
|
|
|
|
tdma = devm_kzalloc(&pdev->dev,
|
|
struct_size(tdma, channels, cdata->nr_channels),
|
|
GFP_KERNEL);
|
|
if (!tdma)
|
|
return -ENOMEM;
|
|
|
|
tdma->dev = &pdev->dev;
|
|
tdma->chip_data = cdata;
|
|
platform_set_drvdata(pdev, tdma);
|
|
|
|
tdma->base_addr = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(tdma->base_addr))
|
|
return PTR_ERR(tdma->base_addr);
|
|
|
|
tdma->rst = devm_reset_control_get_exclusive(&pdev->dev, "gpcdma");
|
|
if (IS_ERR(tdma->rst)) {
|
|
return dev_err_probe(&pdev->dev, PTR_ERR(tdma->rst),
|
|
"Missing controller reset\n");
|
|
}
|
|
reset_control_reset(tdma->rst);
|
|
|
|
tdma->dma_dev.dev = &pdev->dev;
|
|
|
|
iommu_spec = dev_iommu_fwspec_get(&pdev->dev);
|
|
if (!iommu_spec) {
|
|
dev_err(&pdev->dev, "Missing iommu stream-id\n");
|
|
return -EINVAL;
|
|
}
|
|
stream_id = iommu_spec->ids[0] & 0xffff;
|
|
|
|
ret = device_property_read_u32(&pdev->dev, "dma-channel-mask",
|
|
&tdma->chan_mask);
|
|
if (ret) {
|
|
dev_warn(&pdev->dev,
|
|
"Missing dma-channel-mask property, using default channel mask %#x\n",
|
|
TEGRA_GPCDMA_DEFAULT_CHANNEL_MASK);
|
|
tdma->chan_mask = TEGRA_GPCDMA_DEFAULT_CHANNEL_MASK;
|
|
}
|
|
|
|
INIT_LIST_HEAD(&tdma->dma_dev.channels);
|
|
for (i = 0; i < cdata->nr_channels; i++) {
|
|
struct tegra_dma_channel *tdc = &tdma->channels[i];
|
|
|
|
/* Check for channel mask */
|
|
if (!(tdma->chan_mask & BIT(i)))
|
|
continue;
|
|
|
|
tdc->irq = platform_get_irq(pdev, i);
|
|
if (tdc->irq < 0)
|
|
return tdc->irq;
|
|
|
|
tdc->chan_base_offset = TEGRA_GPCDMA_CHANNEL_BASE_ADDR_OFFSET +
|
|
i * cdata->channel_reg_size;
|
|
snprintf(tdc->name, sizeof(tdc->name), "gpcdma.%d", i);
|
|
tdc->tdma = tdma;
|
|
tdc->id = i;
|
|
tdc->slave_id = -1;
|
|
|
|
vchan_init(&tdc->vc, &tdma->dma_dev);
|
|
tdc->vc.desc_free = tegra_dma_desc_free;
|
|
|
|
/* program stream-id for this channel */
|
|
tegra_dma_program_sid(tdc, stream_id);
|
|
tdc->stream_id = stream_id;
|
|
}
|
|
|
|
dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
|
|
dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
|
|
dma_cap_set(DMA_MEMCPY, tdma->dma_dev.cap_mask);
|
|
dma_cap_set(DMA_MEMSET, tdma->dma_dev.cap_mask);
|
|
dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
|
|
|
|
/*
|
|
* Only word aligned transfers are supported. Set the copy
|
|
* alignment shift.
|
|
*/
|
|
tdma->dma_dev.copy_align = 2;
|
|
tdma->dma_dev.fill_align = 2;
|
|
tdma->dma_dev.device_alloc_chan_resources =
|
|
tegra_dma_alloc_chan_resources;
|
|
tdma->dma_dev.device_free_chan_resources =
|
|
tegra_dma_free_chan_resources;
|
|
tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
|
|
tdma->dma_dev.device_prep_dma_memcpy = tegra_dma_prep_dma_memcpy;
|
|
tdma->dma_dev.device_prep_dma_memset = tegra_dma_prep_dma_memset;
|
|
tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic;
|
|
tdma->dma_dev.device_config = tegra_dma_slave_config;
|
|
tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all;
|
|
tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
|
|
tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
|
|
tdma->dma_dev.device_pause = tegra_dma_device_pause;
|
|
tdma->dma_dev.device_resume = tegra_dma_device_resume;
|
|
tdma->dma_dev.device_synchronize = tegra_dma_chan_synchronize;
|
|
tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
|
|
|
|
ret = dma_async_device_register(&tdma->dma_dev);
|
|
if (ret < 0) {
|
|
dev_err_probe(&pdev->dev, ret,
|
|
"GPC DMA driver registration failed\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = of_dma_controller_register(pdev->dev.of_node,
|
|
tegra_dma_of_xlate, tdma);
|
|
if (ret < 0) {
|
|
dev_err_probe(&pdev->dev, ret,
|
|
"GPC DMA OF registration failed\n");
|
|
|
|
dma_async_device_unregister(&tdma->dma_dev);
|
|
return ret;
|
|
}
|
|
|
|
dev_info(&pdev->dev, "GPC DMA driver register %lu channels\n",
|
|
hweight_long(tdma->chan_mask));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_dma_remove(struct platform_device *pdev)
|
|
{
|
|
struct tegra_dma *tdma = platform_get_drvdata(pdev);
|
|
|
|
of_dma_controller_free(pdev->dev.of_node);
|
|
dma_async_device_unregister(&tdma->dma_dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused tegra_dma_pm_suspend(struct device *dev)
|
|
{
|
|
struct tegra_dma *tdma = dev_get_drvdata(dev);
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < tdma->chip_data->nr_channels; i++) {
|
|
struct tegra_dma_channel *tdc = &tdma->channels[i];
|
|
|
|
if (!(tdma->chan_mask & BIT(i)))
|
|
continue;
|
|
|
|
if (tdc->dma_desc) {
|
|
dev_err(tdma->dev, "channel %u busy\n", i);
|
|
return -EBUSY;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused tegra_dma_pm_resume(struct device *dev)
|
|
{
|
|
struct tegra_dma *tdma = dev_get_drvdata(dev);
|
|
unsigned int i;
|
|
|
|
reset_control_reset(tdma->rst);
|
|
|
|
for (i = 0; i < tdma->chip_data->nr_channels; i++) {
|
|
struct tegra_dma_channel *tdc = &tdma->channels[i];
|
|
|
|
if (!(tdma->chan_mask & BIT(i)))
|
|
continue;
|
|
|
|
tegra_dma_program_sid(tdc, tdc->stream_id);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops tegra_dma_dev_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(tegra_dma_pm_suspend, tegra_dma_pm_resume)
|
|
};
|
|
|
|
static struct platform_driver tegra_dma_driver = {
|
|
.driver = {
|
|
.name = "tegra-gpcdma",
|
|
.pm = &tegra_dma_dev_pm_ops,
|
|
.of_match_table = tegra_dma_of_match,
|
|
},
|
|
.probe = tegra_dma_probe,
|
|
.remove = tegra_dma_remove,
|
|
};
|
|
|
|
module_platform_driver(tegra_dma_driver);
|
|
|
|
MODULE_DESCRIPTION("NVIDIA Tegra GPC DMA Controller driver");
|
|
MODULE_AUTHOR("Pavan Kunapuli <pkunapuli@nvidia.com>");
|
|
MODULE_AUTHOR("Rajesh Gumasta <rgumasta@nvidia.com>");
|
|
MODULE_LICENSE("GPL");
|