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499e364cd2
Add the power domain structure for the A3DUL domain (PAP-Subsystem), as described in the R-Car V4H Series Hardware User's Manual Rev. 0.51 and later. Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> [geert: Manual reference] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/14bd8a8de16ced703ff824f6a241e89d1ead6b07.1669740926.git.geert+renesas@glider.be
64 lines
2.5 KiB
C
64 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas R-Car V4H System Controller
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*
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* Copyright (C) 2022 Renesas Electronics Corp.
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*/
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#include <linux/bits.h>
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#include <linux/clk/renesas.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/of_address.h>
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#include <linux/pm_domain.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <dt-bindings/power/r8a779g0-sysc.h>
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#include "rcar-gen4-sysc.h"
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static struct rcar_gen4_sysc_area r8a779g0_areas[] __initdata = {
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{ "always-on", R8A779G0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
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{ "a3e0", R8A779G0_PD_A3E0, R8A779G0_PD_ALWAYS_ON, PD_SCU },
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{ "a2e0d0", R8A779G0_PD_A2E0D0, R8A779G0_PD_A3E0, PD_SCU },
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{ "a2e0d1", R8A779G0_PD_A2E0D1, R8A779G0_PD_A3E0, PD_SCU },
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{ "a1e0d0c0", R8A779G0_PD_A1E0D0C0, R8A779G0_PD_A2E0D0, PD_CPU_NOCR },
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{ "a1e0d0c1", R8A779G0_PD_A1E0D0C1, R8A779G0_PD_A2E0D0, PD_CPU_NOCR },
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{ "a1e0d1c0", R8A779G0_PD_A1E0D1C0, R8A779G0_PD_A2E0D1, PD_CPU_NOCR },
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{ "a1e0d1c1", R8A779G0_PD_A1E0D1C1, R8A779G0_PD_A2E0D1, PD_CPU_NOCR },
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{ "a33dga", R8A779G0_PD_A33DGA, R8A779G0_PD_ALWAYS_ON },
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{ "a23dgb", R8A779G0_PD_A23DGB, R8A779G0_PD_A33DGA },
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{ "a3vip0", R8A779G0_PD_A3VIP0, R8A779G0_PD_ALWAYS_ON },
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{ "a3vip1", R8A779G0_PD_A3VIP1, R8A779G0_PD_ALWAYS_ON },
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{ "a3vip2", R8A779G0_PD_A3VIP2, R8A779G0_PD_ALWAYS_ON },
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{ "a3dul", R8A779G0_PD_A3DUL, R8A779G0_PD_ALWAYS_ON },
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{ "a3isp0", R8A779G0_PD_A3ISP0, R8A779G0_PD_ALWAYS_ON },
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{ "a3isp1", R8A779G0_PD_A3ISP1, R8A779G0_PD_ALWAYS_ON },
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{ "a3ir", R8A779G0_PD_A3IR, R8A779G0_PD_ALWAYS_ON },
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{ "a2cn0", R8A779G0_PD_A2CN0, R8A779G0_PD_A3IR },
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{ "a1cnn0", R8A779G0_PD_A1CNN0, R8A779G0_PD_A2CN0 },
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{ "a1dsp0", R8A779G0_PD_A1DSP0, R8A779G0_PD_A2CN0 },
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{ "a1dsp1", R8A779G0_PD_A1DSP1, R8A779G0_PD_A2CN0 },
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{ "a1dsp2", R8A779G0_PD_A1DSP2, R8A779G0_PD_A2CN0 },
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{ "a1dsp3", R8A779G0_PD_A1DSP3, R8A779G0_PD_A2CN0 },
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{ "a2imp01", R8A779G0_PD_A2IMP01, R8A779G0_PD_A3IR },
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{ "a2imp23", R8A779G0_PD_A2IMP23, R8A779G0_PD_A3IR },
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{ "a2psc", R8A779G0_PD_A2PSC, R8A779G0_PD_A3IR },
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{ "a2dma", R8A779G0_PD_A2DMA, R8A779G0_PD_A3IR },
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{ "a2cv0", R8A779G0_PD_A2CV0, R8A779G0_PD_A3IR },
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{ "a2cv1", R8A779G0_PD_A2CV1, R8A779G0_PD_A3IR },
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{ "a2cv2", R8A779G0_PD_A2CV2, R8A779G0_PD_A3IR },
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{ "a2cv3", R8A779G0_PD_A2CV3, R8A779G0_PD_A3IR },
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};
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const struct rcar_gen4_sysc_info r8a779g0_sysc_info __initconst = {
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.areas = r8a779g0_areas,
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.num_areas = ARRAY_SIZE(r8a779g0_areas),
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};
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