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request_irq() is preferred over setup_irq(). Invocations of setup_irq() occur after memory allocators are ready. Per tglx[1], setup_irq() existed in olden days when allocators were not ready by the time early interrupts were initialized. Hence replace setup_irq() by request_irq(). remove_irq() has been replaced by free_irq() as well. There were build error's during previous version, couple of which was reported by kbuild test robot <lkp@intel.com> of which one was reported by Thomas Bogendoerfer <tsbogend@alpha.franken.de> as well. There were a few more issues including build errors, those also have been fixed. [1] https://lkml.kernel.org/r/alpine.DEB.2.20.1710191609480.1971@nanos Signed-off-by: afzal mohammed <afzal.mohd.ma@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
204 lines
5.2 KiB
C
204 lines
5.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* CS5536 General timer functions
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*
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* Copyright (C) 2007 Lemote Inc. & Institute of Computing Technology
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* Author: Yanhua, yanh@lemote.com
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*
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* Copyright (C) 2009 Lemote Inc.
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* Author: Wu zhangjin, wuzhangjin@gmail.com
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*
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* Reference: AMD Geode(TM) CS5536 Companion Device Data Book
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*/
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#include <linux/io.h>
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#include <linux/init.h>
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#include <linux/export.h>
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#include <linux/jiffies.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/clockchips.h>
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#include <asm/time.h>
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#include <cs5536/cs5536_mfgpt.h>
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static DEFINE_RAW_SPINLOCK(mfgpt_lock);
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static u32 mfgpt_base;
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/*
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* Initialize the MFGPT timer.
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*
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* This is also called after resume to bring the MFGPT into operation again.
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*/
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/* disable counter */
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void disable_mfgpt0_counter(void)
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{
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outw(inw(MFGPT0_SETUP) & 0x7fff, MFGPT0_SETUP);
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}
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EXPORT_SYMBOL(disable_mfgpt0_counter);
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/* enable counter, comparator2 to event mode, 14.318MHz clock */
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void enable_mfgpt0_counter(void)
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{
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outw(0xe310, MFGPT0_SETUP);
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}
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EXPORT_SYMBOL(enable_mfgpt0_counter);
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static int mfgpt_timer_set_periodic(struct clock_event_device *evt)
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{
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raw_spin_lock(&mfgpt_lock);
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outw(COMPARE, MFGPT0_CMP2); /* set comparator2 */
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outw(0, MFGPT0_CNT); /* set counter to 0 */
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enable_mfgpt0_counter();
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raw_spin_unlock(&mfgpt_lock);
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return 0;
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}
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static int mfgpt_timer_shutdown(struct clock_event_device *evt)
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{
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if (clockevent_state_periodic(evt) || clockevent_state_oneshot(evt)) {
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raw_spin_lock(&mfgpt_lock);
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disable_mfgpt0_counter();
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raw_spin_unlock(&mfgpt_lock);
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}
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return 0;
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}
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static struct clock_event_device mfgpt_clockevent = {
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.name = "mfgpt",
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.features = CLOCK_EVT_FEAT_PERIODIC,
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/* The oneshot mode have very high deviation, don't use it! */
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.set_state_shutdown = mfgpt_timer_shutdown,
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.set_state_periodic = mfgpt_timer_set_periodic,
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.irq = CS5536_MFGPT_INTR,
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};
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static irqreturn_t timer_interrupt(int irq, void *dev_id)
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{
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u32 basehi;
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/*
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* get MFGPT base address
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*
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* NOTE: do not remove me, it's need for the value of mfgpt_base is
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* variable
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*/
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_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base);
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/* ack */
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outw(inw(MFGPT0_SETUP) | 0x4000, MFGPT0_SETUP);
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mfgpt_clockevent.event_handler(&mfgpt_clockevent);
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return IRQ_HANDLED;
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}
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/*
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* Initialize the conversion factor and the min/max deltas of the clock event
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* structure and register the clock event source with the framework.
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*/
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void __init setup_mfgpt0_timer(void)
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{
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u32 basehi;
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struct clock_event_device *cd = &mfgpt_clockevent;
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unsigned int cpu = smp_processor_id();
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cd->cpumask = cpumask_of(cpu);
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clockevent_set_clock(cd, MFGPT_TICK_RATE);
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cd->max_delta_ns = clockevent_delta2ns(0xffff, cd);
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cd->max_delta_ticks = 0xffff;
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cd->min_delta_ns = clockevent_delta2ns(0xf, cd);
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cd->min_delta_ticks = 0xf;
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/* Enable MFGPT0 Comparator 2 Output to the Interrupt Mapper */
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_wrmsr(DIVIL_MSR_REG(MFGPT_IRQ), 0, 0x100);
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/* Enable Interrupt Gate 5 */
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_wrmsr(DIVIL_MSR_REG(PIC_ZSEL_LOW), 0, 0x50000);
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/* get MFGPT base address */
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_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base);
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clockevents_register_device(cd);
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if (request_irq(CS5536_MFGPT_INTR, timer_interrupt,
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IRQF_NOBALANCING | IRQF_TIMER, "timer", NULL))
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pr_err("Failed to register timer interrupt\n");
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}
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/*
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* Since the MFGPT overflows every tick, its not very useful
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* to just read by itself. So use jiffies to emulate a free
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* running counter:
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*/
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static u64 mfgpt_read(struct clocksource *cs)
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{
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unsigned long flags;
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int count;
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u32 jifs;
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static int old_count;
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static u32 old_jifs;
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raw_spin_lock_irqsave(&mfgpt_lock, flags);
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/*
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* Although our caller may have the read side of xtime_lock,
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* this is now a seqlock, and we are cheating in this routine
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* by having side effects on state that we cannot undo if
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* there is a collision on the seqlock and our caller has to
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* retry. (Namely, old_jifs and old_count.) So we must treat
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* jiffies as volatile despite the lock. We read jiffies
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* before latching the timer count to guarantee that although
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* the jiffies value might be older than the count (that is,
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* the counter may underflow between the last point where
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* jiffies was incremented and the point where we latch the
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* count), it cannot be newer.
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*/
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jifs = jiffies;
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/* read the count */
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count = inw(MFGPT0_CNT);
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/*
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* It's possible for count to appear to go the wrong way for this
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* reason:
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*
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* The timer counter underflows, but we haven't handled the resulting
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* interrupt and incremented jiffies yet.
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*
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* Previous attempts to handle these cases intelligently were buggy, so
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* we just do the simple thing now.
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*/
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if (count < old_count && jifs == old_jifs)
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count = old_count;
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old_count = count;
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old_jifs = jifs;
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raw_spin_unlock_irqrestore(&mfgpt_lock, flags);
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return (u64) (jifs * COMPARE) + count;
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}
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static struct clocksource clocksource_mfgpt = {
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.name = "mfgpt",
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.rating = 120, /* Functional for real use, but not desired */
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.read = mfgpt_read,
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.mask = CLOCKSOURCE_MASK(32),
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};
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int __init init_mfgpt_clocksource(void)
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{
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if (num_possible_cpus() > 1) /* MFGPT does not scale! */
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return 0;
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return clocksource_register_hz(&clocksource_mfgpt, MFGPT_TICK_RATE);
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}
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arch_initcall(init_mfgpt_clocksource);
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