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356bd1460d
Signed-off-by: Francois Romieu <romieu@fr.zoreil.com>
177 lines
4.2 KiB
C
177 lines
4.2 KiB
C
/* $Date: 2006/02/07 04:21:54 $ $RCSfile: tp.c,v $ $Revision: 1.73 $ */
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#include "common.h"
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#include "regs.h"
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#include "tp.h"
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#ifdef CONFIG_CHELSIO_T1_1G
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#include "fpga_defs.h"
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#endif
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struct petp {
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adapter_t *adapter;
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};
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/* Pause deadlock avoidance parameters */
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#define DROP_MSEC 16
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#define DROP_PKTS_CNT 1
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static void tp_init(adapter_t * ap, const struct tp_params *p,
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unsigned int tp_clk)
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{
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u32 val;
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if (!t1_is_asic(ap))
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return;
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val = F_TP_IN_CSPI_CPL | F_TP_IN_CSPI_CHECK_IP_CSUM |
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F_TP_IN_CSPI_CHECK_TCP_CSUM | F_TP_IN_ESPI_ETHERNET;
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if (!p->pm_size)
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val |= F_OFFLOAD_DISABLE;
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else
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val |= F_TP_IN_ESPI_CHECK_IP_CSUM | F_TP_IN_ESPI_CHECK_TCP_CSUM;
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writel(val, ap->regs + A_TP_IN_CONFIG);
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writel(F_TP_OUT_CSPI_CPL |
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F_TP_OUT_ESPI_ETHERNET |
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F_TP_OUT_ESPI_GENERATE_IP_CSUM |
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F_TP_OUT_ESPI_GENERATE_TCP_CSUM, ap->regs + A_TP_OUT_CONFIG);
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writel(V_IP_TTL(64) |
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F_PATH_MTU /* IP DF bit */ |
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V_5TUPLE_LOOKUP(p->use_5tuple_mode) |
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V_SYN_COOKIE_PARAMETER(29), ap->regs + A_TP_GLOBAL_CONFIG);
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/*
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* Enable pause frame deadlock prevention.
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*/
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if (is_T2(ap) && ap->params.nports > 1) {
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u32 drop_ticks = DROP_MSEC * (tp_clk / 1000);
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writel(F_ENABLE_TX_DROP | F_ENABLE_TX_ERROR |
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V_DROP_TICKS_CNT(drop_ticks) |
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V_NUM_PKTS_DROPPED(DROP_PKTS_CNT),
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ap->regs + A_TP_TX_DROP_CONFIG);
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}
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}
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void t1_tp_destroy(struct petp *tp)
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{
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kfree(tp);
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}
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struct petp *__devinit t1_tp_create(adapter_t * adapter, struct tp_params *p)
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{
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struct petp *tp = kzalloc(sizeof(*tp), GFP_KERNEL);
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if (!tp)
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return NULL;
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tp->adapter = adapter;
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return tp;
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}
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void t1_tp_intr_enable(struct petp *tp)
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{
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u32 tp_intr = readl(tp->adapter->regs + A_PL_ENABLE);
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#ifdef CONFIG_CHELSIO_T1_1G
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if (!t1_is_asic(tp->adapter)) {
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/* FPGA */
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writel(0xffffffff,
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tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE);
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writel(tp_intr | FPGA_PCIX_INTERRUPT_TP,
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tp->adapter->regs + A_PL_ENABLE);
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} else
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#endif
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{
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/* We don't use any TP interrupts */
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writel(0, tp->adapter->regs + A_TP_INT_ENABLE);
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writel(tp_intr | F_PL_INTR_TP,
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tp->adapter->regs + A_PL_ENABLE);
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}
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}
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void t1_tp_intr_disable(struct petp *tp)
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{
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u32 tp_intr = readl(tp->adapter->regs + A_PL_ENABLE);
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#ifdef CONFIG_CHELSIO_T1_1G
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if (!t1_is_asic(tp->adapter)) {
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/* FPGA */
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writel(0, tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE);
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writel(tp_intr & ~FPGA_PCIX_INTERRUPT_TP,
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tp->adapter->regs + A_PL_ENABLE);
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} else
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#endif
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{
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writel(0, tp->adapter->regs + A_TP_INT_ENABLE);
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writel(tp_intr & ~F_PL_INTR_TP,
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tp->adapter->regs + A_PL_ENABLE);
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}
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}
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void t1_tp_intr_clear(struct petp *tp)
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{
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#ifdef CONFIG_CHELSIO_T1_1G
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if (!t1_is_asic(tp->adapter)) {
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writel(0xffffffff,
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tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
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writel(FPGA_PCIX_INTERRUPT_TP, tp->adapter->regs + A_PL_CAUSE);
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return;
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}
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#endif
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writel(0xffffffff, tp->adapter->regs + A_TP_INT_CAUSE);
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writel(F_PL_INTR_TP, tp->adapter->regs + A_PL_CAUSE);
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}
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int t1_tp_intr_handler(struct petp *tp)
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{
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u32 cause;
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#ifdef CONFIG_CHELSIO_T1_1G
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/* FPGA doesn't support TP interrupts. */
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if (!t1_is_asic(tp->adapter))
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return 1;
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#endif
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cause = readl(tp->adapter->regs + A_TP_INT_CAUSE);
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writel(cause, tp->adapter->regs + A_TP_INT_CAUSE);
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return 0;
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}
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static void set_csum_offload(struct petp *tp, u32 csum_bit, int enable)
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{
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u32 val = readl(tp->adapter->regs + A_TP_GLOBAL_CONFIG);
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if (enable)
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val |= csum_bit;
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else
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val &= ~csum_bit;
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writel(val, tp->adapter->regs + A_TP_GLOBAL_CONFIG);
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}
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void t1_tp_set_ip_checksum_offload(struct petp *tp, int enable)
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{
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set_csum_offload(tp, F_IP_CSUM, enable);
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}
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void t1_tp_set_udp_checksum_offload(struct petp *tp, int enable)
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{
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set_csum_offload(tp, F_UDP_CSUM, enable);
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}
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void t1_tp_set_tcp_checksum_offload(struct petp *tp, int enable)
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{
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set_csum_offload(tp, F_TCP_CSUM, enable);
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}
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/*
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* Initialize TP state. tp_params contains initial settings for some TP
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* parameters, particularly the one-time PM and CM settings.
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*/
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int t1_tp_reset(struct petp *tp, struct tp_params *p, unsigned int tp_clk)
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{
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adapter_t *adapter = tp->adapter;
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tp_init(adapter, p, tp_clk);
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writel(F_TP_RESET, adapter->regs + A_TP_RESET);
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return 0;
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}
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