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fce152a63d
Update all 32bit rockchip devicetree files to use SPDX-License-Identifiers. All files except rk3288-veyron-analog-audio.dtsi (which is GPL 2.0 only) claim to be GPL and X11 while the actual license text is MIT. Use the MIT SPDX tag for them. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Acked-by: Brian Norris <briannorris@chromium.org> Acked-by: Matthias Brugger <mbrugger@suse.com> Acked-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
177 lines
4.1 KiB
Plaintext
177 lines
4.1 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Google Veyron Jaq Rev 1+ board device tree source
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*
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* Copyright 2015 Google, Inc
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*/
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/dts-v1/;
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#include "rk3288-veyron-chromebook.dtsi"
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#include "cros-ec-sbs.dtsi"
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/ {
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model = "Google Jaq";
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compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4",
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"google,veyron-jaq-rev3", "google,veyron-jaq-rev2",
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"google,veyron-jaq-rev1", "google,veyron-jaq",
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"google,veyron", "rockchip,rk3288";
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panel_regulator: panel-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&lcd_enable_h>;
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regulator-name = "panel_regulator";
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startup-delay-us = <100000>;
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vin-supply = <&vcc33_sys>;
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};
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vcc18_lcd: vcc18-lcd {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&avdd_1v8_disp_en>;
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regulator-name = "vcc18_lcd";
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regulator-always-on;
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regulator-boot-on;
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vin-supply = <&vcc18_wl>;
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};
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backlight_regulator: backlight-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&bl_pwr_en>;
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regulator-name = "backlight_regulator";
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vin-supply = <&vcc33_sys>;
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startup-delay-us = <15000>;
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};
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};
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&backlight {
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/* Jaq panel PWM must be >= 3%, so start non-zero brightness at 8 */
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brightness-levels = <
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0
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8 9 10 11 12 13 14 15
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16 17 18 19 20 21 22 23
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24 25 26 27 28 29 30 31
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32 33 34 35 36 37 38 39
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40 41 42 43 44 45 46 47
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48 49 50 51 52 53 54 55
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56 57 58 59 60 61 62 63
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64 65 66 67 68 69 70 71
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72 73 74 75 76 77 78 79
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80 81 82 83 84 85 86 87
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88 89 90 91 92 93 94 95
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96 97 98 99 100 101 102 103
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104 105 106 107 108 109 110 111
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112 113 114 115 116 117 118 119
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120 121 122 123 124 125 126 127
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128 129 130 131 132 133 134 135
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136 137 138 139 140 141 142 143
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144 145 146 147 148 149 150 151
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152 153 154 155 156 157 158 159
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160 161 162 163 164 165 166 167
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168 169 170 171 172 173 174 175
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176 177 178 179 180 181 182 183
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184 185 186 187 188 189 190 191
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192 193 194 195 196 197 198 199
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200 201 202 203 204 205 206 207
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208 209 210 211 212 213 214 215
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216 217 218 219 220 221 222 223
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224 225 226 227 228 229 230 231
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232 233 234 235 236 237 238 239
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240 241 242 243 244 245 246 247
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248 249 250 251 252 253 254 255>;
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power-supply = <&backlight_regulator>;
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};
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&panel {
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power-supply = <&panel_regulator>;
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};
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&rk808 {
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pinctrl-names = "default";
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pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
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dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
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<&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
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regulators {
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mic_vcc: LDO_REG2 {
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regulator-name = "mic_vcc";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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};
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};
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&sdmmc {
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disable-wp;
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
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&sdmmc_bus4>;
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};
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&vcc_5v {
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enable-active-high;
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gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&drv_5v>;
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};
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&vcc50_hdmi {
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enable-active-high;
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gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&vcc50_hdmi_en>;
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};
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&pinctrl {
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backlight {
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bl_pwr_en: bl_pwr_en {
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rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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buck-5v {
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drv_5v: drv-5v {
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rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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hdmi {
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vcc50_hdmi_en: vcc50-hdmi-en {
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rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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lcd {
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lcd_enable_h: lcd-en {
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rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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avdd_1v8_disp_en: avdd-1v8-disp-en {
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rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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pmic {
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dvs_1: dvs-1 {
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rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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dvs_2: dvs-2 {
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rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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};
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};
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