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4c38798461
Similar to commit 8f42cb7f64 ("ARM: dts: omap4: Add l4 interconnect
hierarchy and ti-sysc data"), let's add proper interconnect hierarchy
for l4 interconnect instances with the related ti-sysc interconnect
module data as in Documentation/devicetree/bindings/bus/ti-sysc.txt.
Using ti-sysc driver binding allows us to start dropping legacy platform
data in arch/arm/mach-omap2/omap*hwmod*data.c files later on in favor of
ti-sysc dts data.
This data is generated based on platform data from a booted system
and the interconnect acces protection registers for ranges. To avoid
regressions, we initially validate the device tree provided data
against the existing platform data on boot.
Cc: devicetree@vger.kernel.org
Signed-off-by: Tony Lindgren <tony@atomide.com>
520 lines
13 KiB
Plaintext
520 lines
13 KiB
Plaintext
/*
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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* Based on "omap4.dtsi"
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*/
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#include <dt-bindings/bus/ti-sysc.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/omap.h>
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#include <dt-bindings/clock/omap5.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "ti,omap5";
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interrupt-parent = <&wakeupgen>;
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chosen { };
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aliases {
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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i2c3 = &i2c4;
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i2c4 = &i2c5;
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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serial5 = &uart6;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x0>;
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operating-points = <
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/* kHz uV */
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1000000 1060000
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1500000 1250000
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>;
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clocks = <&dpll_mpu_ck>;
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clock-names = "cpu";
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clock-latency = <300000>; /* From omap-cpufreq driver */
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/* cooling options */
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x1>;
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operating-points = <
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/* kHz uV */
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1000000 1060000
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1500000 1250000
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>;
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clocks = <&dpll_mpu_ck>;
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clock-names = "cpu";
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clock-latency = <300000>; /* From omap-cpufreq driver */
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/* cooling options */
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#cooling-cells = <2>; /* min followed by max */
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};
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};
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thermal-zones {
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#include "omap4-cpu-thermal.dtsi"
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#include "omap5-gpu-thermal.dtsi"
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#include "omap5-core-thermal.dtsi"
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};
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timer {
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compatible = "arm,armv7-timer";
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/* PPI secure/nonsecure IRQ */
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
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interrupt-parent = <&gic>;
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};
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pmu {
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compatible = "arm,cortex-a15-pmu";
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interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
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};
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gic: interrupt-controller@48211000 {
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compatible = "arm,cortex-a15-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0 0x48211000 0 0x1000>,
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<0 0x48212000 0 0x2000>,
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<0 0x48214000 0 0x2000>,
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<0 0x48216000 0 0x2000>;
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interrupt-parent = <&gic>;
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};
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wakeupgen: interrupt-controller@48281000 {
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compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0 0x48281000 0 0x1000>;
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interrupt-parent = <&gic>;
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};
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/*
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* The soc node represents the soc top level view. It is used for IPs
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* that are not memory mapped in the MPU view or for the MPU itself.
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*/
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soc {
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compatible = "ti,omap-infra";
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mpu {
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compatible = "ti,omap4-mpu";
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ti,hwmods = "mpu";
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sram = <&ocmcram>;
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};
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};
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/*
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* XXX: Use a flat representation of the OMAP3 interconnect.
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* The real OMAP interconnect network is quite complex.
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* Since it will not bring real advantage to represent that in DT for
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* the moment, just use a fake OCP bus entry to represent the whole bus
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* hierarchy.
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*/
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ocp {
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compatible = "ti,omap5-l3-noc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xc0000000>;
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ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
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reg = <0 0x44000000 0 0x2000>,
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<0 0x44800000 0 0x3000>,
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<0 0x45000000 0 0x4000>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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l4_wkup: interconnect@4ae00000 {
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};
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l4_cfg: interconnect@4a000000 {
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};
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l4_per: interconnect@48000000 {
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};
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ocmcram: ocmcram@40300000 {
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compatible = "mmio-sram";
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reg = <0x40300000 0x20000>; /* 128k */
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};
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gpmc: gpmc@50000000 {
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compatible = "ti,omap4430-gpmc";
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reg = <0x50000000 0x1000>;
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#address-cells = <2>;
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#size-cells = <1>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&sdma 4>;
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dma-names = "rxtx";
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gpmc,num-cs = <8>;
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gpmc,num-waitpins = <4>;
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ti,hwmods = "gpmc";
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clocks = <&l3_iclk_div>;
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clock-names = "fck";
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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mmu_dsp: mmu@4a066000 {
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compatible = "ti,omap4-iommu";
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reg = <0x4a066000 0x100>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "mmu_dsp";
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#iommu-cells = <0>;
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};
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mmu_ipu: mmu@55082000 {
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compatible = "ti,omap4-iommu";
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reg = <0x55082000 0x100>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "mmu_ipu";
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#iommu-cells = <0>;
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ti,iommu-bus-err-back;
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};
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mcpdm: mcpdm@40132000 {
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compatible = "ti,omap4-mcpdm";
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reg = <0x40132000 0x7f>, /* MPU private access */
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<0x49032000 0x7f>; /* L3 Interconnect */
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reg-names = "mpu", "dma";
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "mcpdm";
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dmas = <&sdma 65>,
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<&sdma 66>;
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dma-names = "up_link", "dn_link";
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status = "disabled";
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};
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dmic: dmic@4012e000 {
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compatible = "ti,omap4-dmic";
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reg = <0x4012e000 0x7f>, /* MPU private access */
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<0x4902e000 0x7f>; /* L3 Interconnect */
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reg-names = "mpu", "dma";
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interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "dmic";
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dmas = <&sdma 67>;
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dma-names = "up_link";
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status = "disabled";
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};
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mcbsp1: mcbsp@40122000 {
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compatible = "ti,omap4-mcbsp";
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reg = <0x40122000 0xff>, /* MPU private access */
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<0x49022000 0xff>; /* L3 Interconnect */
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reg-names = "mpu", "dma";
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "common";
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ti,buffer-size = <128>;
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ti,hwmods = "mcbsp1";
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dmas = <&sdma 33>,
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<&sdma 34>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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mcbsp2: mcbsp@40124000 {
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compatible = "ti,omap4-mcbsp";
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reg = <0x40124000 0xff>, /* MPU private access */
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<0x49024000 0xff>; /* L3 Interconnect */
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reg-names = "mpu", "dma";
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "common";
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ti,buffer-size = <128>;
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ti,hwmods = "mcbsp2";
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dmas = <&sdma 17>,
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<&sdma 18>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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mcbsp3: mcbsp@40126000 {
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compatible = "ti,omap4-mcbsp";
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reg = <0x40126000 0xff>, /* MPU private access */
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<0x49026000 0xff>; /* L3 Interconnect */
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reg-names = "mpu", "dma";
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "common";
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ti,buffer-size = <128>;
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ti,hwmods = "mcbsp3";
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dmas = <&sdma 19>,
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<&sdma 20>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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timer5: timer@40138000 {
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compatible = "ti,omap5430-timer";
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reg = <0x40138000 0x80>,
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<0x49038000 0x80>;
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interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "timer5";
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ti,timer-dsp;
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ti,timer-pwm;
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};
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timer6: timer@4013a000 {
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compatible = "ti,omap5430-timer";
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reg = <0x4013a000 0x80>,
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<0x4903a000 0x80>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "timer6";
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ti,timer-dsp;
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ti,timer-pwm;
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};
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timer7: timer@4013c000 {
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compatible = "ti,omap5430-timer";
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reg = <0x4013c000 0x80>,
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<0x4903c000 0x80>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "timer7";
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ti,timer-dsp;
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};
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timer8: timer@4013e000 {
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compatible = "ti,omap5430-timer";
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reg = <0x4013e000 0x80>,
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<0x4903e000 0x80>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "timer8";
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ti,timer-dsp;
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ti,timer-pwm;
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};
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dmm@4e000000 {
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compatible = "ti,omap5-dmm";
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reg = <0x4e000000 0x800>;
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interrupts = <0 113 0x4>;
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ti,hwmods = "dmm";
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};
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emif1: emif@4c000000 {
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compatible = "ti,emif-4d5";
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ti,hwmods = "emif1";
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ti,no-idle-on-init;
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phy-type = <2>; /* DDR PHY type: Intelli PHY */
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reg = <0x4c000000 0x400>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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hw-caps-read-idle-ctrl;
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hw-caps-ll-interface;
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hw-caps-temp-alert;
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};
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emif2: emif@4d000000 {
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compatible = "ti,emif-4d5";
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ti,hwmods = "emif2";
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ti,no-idle-on-init;
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phy-type = <2>; /* DDR PHY type: Intelli PHY */
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reg = <0x4d000000 0x400>;
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interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
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hw-caps-read-idle-ctrl;
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hw-caps-ll-interface;
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hw-caps-temp-alert;
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};
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bandgap: bandgap@4a0021e0 {
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reg = <0x4a0021e0 0xc
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0x4a00232c 0xc
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0x4a002380 0x2c
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0x4a0023C0 0x3c>;
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interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
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compatible = "ti,omap5430-bandgap";
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#thermal-sensor-cells = <1>;
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};
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/* OCP2SCP3 */
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sata: sata@4a141100 {
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compatible = "snps,dwc-ahci";
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reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&sata_phy>;
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phy-names = "sata-phy";
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clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
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ti,hwmods = "sata";
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ports-implemented = <0x1>;
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};
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dss: dss@58000000 {
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compatible = "ti,omap5-dss";
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reg = <0x58000000 0x80>;
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status = "disabled";
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ti,hwmods = "dss_core";
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clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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dispc@58001000 {
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compatible = "ti,omap5-dispc";
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reg = <0x58001000 0x1000>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "dss_dispc";
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clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
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clock-names = "fck";
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};
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rfbi: encoder@58002000 {
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compatible = "ti,omap5-rfbi";
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reg = <0x58002000 0x100>;
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status = "disabled";
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ti,hwmods = "dss_rfbi";
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clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
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clock-names = "fck", "ick";
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};
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dsi1: encoder@58004000 {
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compatible = "ti,omap5-dsi";
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reg = <0x58004000 0x200>,
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<0x58004200 0x40>,
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<0x58004300 0x40>;
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reg-names = "proto", "phy", "pll";
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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ti,hwmods = "dss_dsi1";
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clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
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<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
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clock-names = "fck", "sys_clk";
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};
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dsi2: encoder@58005000 {
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compatible = "ti,omap5-dsi";
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reg = <0x58009000 0x200>,
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<0x58009200 0x40>,
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<0x58009300 0x40>;
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reg-names = "proto", "phy", "pll";
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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ti,hwmods = "dss_dsi2";
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clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
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<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
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clock-names = "fck", "sys_clk";
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};
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hdmi: encoder@58060000 {
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compatible = "ti,omap5-hdmi";
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reg = <0x58040000 0x200>,
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<0x58040200 0x80>,
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<0x58040300 0x80>,
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<0x58060000 0x19000>;
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reg-names = "wp", "pll", "phy", "core";
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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ti,hwmods = "dss_hdmi";
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clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
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<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
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clock-names = "fck", "sys_clk";
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dmas = <&sdma 76>;
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dma-names = "audio_tx";
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};
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};
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abb_mpu: regulator-abb-mpu {
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compatible = "ti,abb-v2";
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regulator-name = "abb_mpu";
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#address-cells = <0>;
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#size-cells = <0>;
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clocks = <&sys_clkin>;
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ti,settling-time = <50>;
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ti,clock-cycles = <16>;
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reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
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<0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
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reg-names = "base-address", "int-address",
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"efuse-address", "ldo-address";
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ti,tranxdone-status-mask = <0x80>;
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/* LDOVBBMPU_MUX_CTRL */
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ti,ldovbb-override-mask = <0x400>;
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/* LDOVBBMPU_VSET_OUT */
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ti,ldovbb-vset-mask = <0x1F>;
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|
/*
|
|
* NOTE: only FBB mode used but actual vset will
|
|
* determine final biasing
|
|
*/
|
|
ti,abb_info = <
|
|
/*uV ABB efuse rbb_m fbb_m vset_m*/
|
|
1060000 0 0x0 0 0x02000000 0x01F00000
|
|
1250000 0 0x4 0 0x02000000 0x01F00000
|
|
>;
|
|
};
|
|
|
|
abb_mm: regulator-abb-mm {
|
|
compatible = "ti,abb-v2";
|
|
regulator-name = "abb_mm";
|
|
#address-cells = <0>;
|
|
#size-cells = <0>;
|
|
clocks = <&sys_clkin>;
|
|
ti,settling-time = <50>;
|
|
ti,clock-cycles = <16>;
|
|
|
|
reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
|
|
<0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
|
|
reg-names = "base-address", "int-address",
|
|
"efuse-address", "ldo-address";
|
|
ti,tranxdone-status-mask = <0x80000000>;
|
|
/* LDOVBBMM_MUX_CTRL */
|
|
ti,ldovbb-override-mask = <0x400>;
|
|
/* LDOVBBMM_VSET_OUT */
|
|
ti,ldovbb-vset-mask = <0x1F>;
|
|
|
|
/*
|
|
* NOTE: only FBB mode used but actual vset will
|
|
* determine final biasing
|
|
*/
|
|
ti,abb_info = <
|
|
/*uV ABB efuse rbb_m fbb_m vset_m*/
|
|
1025000 0 0x0 0 0x02000000 0x01F00000
|
|
1120000 0 0x4 0 0x02000000 0x01F00000
|
|
>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&cpu_thermal {
|
|
polling-delay = <500>; /* milliseconds */
|
|
coefficients = <65 (-1791)>;
|
|
};
|
|
|
|
#include "omap5-l4.dtsi"
|
|
#include "omap54xx-clocks.dtsi"
|
|
|
|
&gpu_thermal {
|
|
coefficients = <117 (-2992)>;
|
|
};
|
|
|
|
&core_thermal {
|
|
coefficients = <0 2000>;
|
|
};
|