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2b254693be
Now that the additional enable bits in the enet PLL are handled as gates, the gate_mask is identical for all plls. Remove the gate_mask from the code and use the BM_PLL_ENABLE bit for enabling/disabling the PLL. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org>
84 lines
2.4 KiB
C
84 lines
2.4 KiB
C
#ifndef __MACH_IMX_CLK_H
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#define __MACH_IMX_CLK_H
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#include <linux/spinlock.h>
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#include <linux/clk-provider.h>
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extern spinlock_t imx_ccm_lock;
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struct clk *imx_clk_pllv1(const char *name, const char *parent,
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void __iomem *base);
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struct clk *imx_clk_pllv2(const char *name, const char *parent,
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void __iomem *base);
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enum imx_pllv3_type {
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IMX_PLLV3_GENERIC,
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IMX_PLLV3_SYS,
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IMX_PLLV3_USB,
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IMX_PLLV3_AV,
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IMX_PLLV3_ENET,
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IMX_PLLV3_MLB,
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};
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struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
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const char *parent_name, void __iomem *base, u32 div_mask);
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struct clk *clk_register_gate2(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 bit_idx,
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u8 clk_gate_flags, spinlock_t *lock);
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static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
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shift, 0, &imx_ccm_lock);
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}
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struct clk *imx_clk_pfd(const char *name, const char *parent_name,
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void __iomem *reg, u8 idx);
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struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
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void __iomem *reg, u8 shift, u8 width,
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void __iomem *busy_reg, u8 busy_shift);
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struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
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u8 width, void __iomem *busy_reg, u8 busy_shift,
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const char **parent_names, int num_parents);
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static inline struct clk *imx_clk_fixed(const char *name, int rate)
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{
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return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
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}
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static inline struct clk *imx_clk_divider(const char *name, const char *parent,
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void __iomem *reg, u8 shift, u8 width)
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{
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return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
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reg, shift, width, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_gate(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
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shift, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
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u8 shift, u8 width, const char **parents, int num_parents)
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{
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return clk_register_mux(NULL, name, parents, num_parents, 0, reg, shift,
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width, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_fixed_factor(const char *name,
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const char *parent, unsigned int mult, unsigned int div)
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{
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return clk_register_fixed_factor(NULL, name, parent,
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CLK_SET_RATE_PARENT, mult, div);
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}
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#endif
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