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ef74b5bf22
RAPL MSRs and handling for Cannon Lake are similar to Sky Lake and Kaby Lake. Signed-off-by: Joe Konno <joe.konno@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
1680 lines
43 KiB
C
1680 lines
43 KiB
C
/*
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* Intel Running Average Power Limit (RAPL) Driver
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* Copyright (c) 2013, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.
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*
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/list.h>
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#include <linux/types.h>
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#include <linux/device.h>
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#include <linux/slab.h>
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#include <linux/log2.h>
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#include <linux/bitmap.h>
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#include <linux/delay.h>
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#include <linux/sysfs.h>
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#include <linux/cpu.h>
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#include <linux/powercap.h>
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#include <linux/suspend.h>
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#include <asm/iosf_mbi.h>
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#include <asm/processor.h>
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#include <asm/cpu_device_id.h>
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#include <asm/intel-family.h>
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/* Local defines */
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#define MSR_PLATFORM_POWER_LIMIT 0x0000065C
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/* bitmasks for RAPL MSRs, used by primitive access functions */
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#define ENERGY_STATUS_MASK 0xffffffff
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#define POWER_LIMIT1_MASK 0x7FFF
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#define POWER_LIMIT1_ENABLE BIT(15)
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#define POWER_LIMIT1_CLAMP BIT(16)
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#define POWER_LIMIT2_MASK (0x7FFFULL<<32)
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#define POWER_LIMIT2_ENABLE BIT_ULL(47)
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#define POWER_LIMIT2_CLAMP BIT_ULL(48)
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#define POWER_PACKAGE_LOCK BIT_ULL(63)
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#define POWER_PP_LOCK BIT(31)
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#define TIME_WINDOW1_MASK (0x7FULL<<17)
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#define TIME_WINDOW2_MASK (0x7FULL<<49)
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#define POWER_UNIT_OFFSET 0
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#define POWER_UNIT_MASK 0x0F
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#define ENERGY_UNIT_OFFSET 0x08
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#define ENERGY_UNIT_MASK 0x1F00
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#define TIME_UNIT_OFFSET 0x10
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#define TIME_UNIT_MASK 0xF0000
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#define POWER_INFO_MAX_MASK (0x7fffULL<<32)
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#define POWER_INFO_MIN_MASK (0x7fffULL<<16)
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#define POWER_INFO_MAX_TIME_WIN_MASK (0x3fULL<<48)
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#define POWER_INFO_THERMAL_SPEC_MASK 0x7fff
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#define PERF_STATUS_THROTTLE_TIME_MASK 0xffffffff
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#define PP_POLICY_MASK 0x1F
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/* Non HW constants */
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#define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */
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#define RAPL_PRIMITIVE_DUMMY BIT(2)
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#define TIME_WINDOW_MAX_MSEC 40000
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#define TIME_WINDOW_MIN_MSEC 250
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#define ENERGY_UNIT_SCALE 1000 /* scale from driver unit to powercap unit */
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enum unit_type {
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ARBITRARY_UNIT, /* no translation */
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POWER_UNIT,
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ENERGY_UNIT,
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TIME_UNIT,
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};
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enum rapl_domain_type {
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RAPL_DOMAIN_PACKAGE, /* entire package/socket */
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RAPL_DOMAIN_PP0, /* core power plane */
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RAPL_DOMAIN_PP1, /* graphics uncore */
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RAPL_DOMAIN_DRAM,/* DRAM control_type */
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RAPL_DOMAIN_PLATFORM, /* PSys control_type */
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RAPL_DOMAIN_MAX,
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};
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enum rapl_domain_msr_id {
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RAPL_DOMAIN_MSR_LIMIT,
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RAPL_DOMAIN_MSR_STATUS,
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RAPL_DOMAIN_MSR_PERF,
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RAPL_DOMAIN_MSR_POLICY,
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RAPL_DOMAIN_MSR_INFO,
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RAPL_DOMAIN_MSR_MAX,
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};
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/* per domain data, some are optional */
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enum rapl_primitives {
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ENERGY_COUNTER,
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POWER_LIMIT1,
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POWER_LIMIT2,
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FW_LOCK,
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PL1_ENABLE, /* power limit 1, aka long term */
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PL1_CLAMP, /* allow frequency to go below OS request */
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PL2_ENABLE, /* power limit 2, aka short term, instantaneous */
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PL2_CLAMP,
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TIME_WINDOW1, /* long term */
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TIME_WINDOW2, /* short term */
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THERMAL_SPEC_POWER,
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MAX_POWER,
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MIN_POWER,
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MAX_TIME_WINDOW,
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THROTTLED_TIME,
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PRIORITY_LEVEL,
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/* below are not raw primitive data */
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AVERAGE_POWER,
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NR_RAPL_PRIMITIVES,
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};
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#define NR_RAW_PRIMITIVES (NR_RAPL_PRIMITIVES - 2)
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/* Can be expanded to include events, etc.*/
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struct rapl_domain_data {
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u64 primitives[NR_RAPL_PRIMITIVES];
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unsigned long timestamp;
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};
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struct msrl_action {
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u32 msr_no;
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u64 clear_mask;
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u64 set_mask;
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int err;
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};
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#define DOMAIN_STATE_INACTIVE BIT(0)
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#define DOMAIN_STATE_POWER_LIMIT_SET BIT(1)
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#define DOMAIN_STATE_BIOS_LOCKED BIT(2)
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#define NR_POWER_LIMITS (2)
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struct rapl_power_limit {
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struct powercap_zone_constraint *constraint;
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int prim_id; /* primitive ID used to enable */
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struct rapl_domain *domain;
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const char *name;
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u64 last_power_limit;
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};
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static const char pl1_name[] = "long_term";
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static const char pl2_name[] = "short_term";
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struct rapl_package;
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struct rapl_domain {
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const char *name;
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enum rapl_domain_type id;
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int msrs[RAPL_DOMAIN_MSR_MAX];
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struct powercap_zone power_zone;
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struct rapl_domain_data rdd;
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struct rapl_power_limit rpl[NR_POWER_LIMITS];
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u64 attr_map; /* track capabilities */
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unsigned int state;
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unsigned int domain_energy_unit;
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struct rapl_package *rp;
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};
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#define power_zone_to_rapl_domain(_zone) \
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container_of(_zone, struct rapl_domain, power_zone)
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/* Each physical package contains multiple domains, these are the common
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* data across RAPL domains within a package.
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*/
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struct rapl_package {
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unsigned int id; /* physical package/socket id */
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unsigned int nr_domains;
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unsigned long domain_map; /* bit map of active domains */
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unsigned int power_unit;
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unsigned int energy_unit;
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unsigned int time_unit;
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struct rapl_domain *domains; /* array of domains, sized at runtime */
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struct powercap_zone *power_zone; /* keep track of parent zone */
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unsigned long power_limit_irq; /* keep track of package power limit
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* notify interrupt enable status.
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*/
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struct list_head plist;
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int lead_cpu; /* one active cpu per package for access */
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/* Track active cpus */
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struct cpumask cpumask;
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};
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struct rapl_defaults {
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u8 floor_freq_reg_addr;
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int (*check_unit)(struct rapl_package *rp, int cpu);
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void (*set_floor_freq)(struct rapl_domain *rd, bool mode);
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u64 (*compute_time_window)(struct rapl_package *rp, u64 val,
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bool to_raw);
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unsigned int dram_domain_energy_unit;
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};
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static struct rapl_defaults *rapl_defaults;
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/* Sideband MBI registers */
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#define IOSF_CPU_POWER_BUDGET_CTL_BYT (0x2)
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#define IOSF_CPU_POWER_BUDGET_CTL_TNG (0xdf)
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#define PACKAGE_PLN_INT_SAVED BIT(0)
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#define MAX_PRIM_NAME (32)
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/* per domain data. used to describe individual knobs such that access function
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* can be consolidated into one instead of many inline functions.
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*/
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struct rapl_primitive_info {
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const char *name;
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u64 mask;
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int shift;
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enum rapl_domain_msr_id id;
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enum unit_type unit;
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u32 flag;
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};
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#define PRIMITIVE_INFO_INIT(p, m, s, i, u, f) { \
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.name = #p, \
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.mask = m, \
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.shift = s, \
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.id = i, \
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.unit = u, \
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.flag = f \
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}
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static void rapl_init_domains(struct rapl_package *rp);
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static int rapl_read_data_raw(struct rapl_domain *rd,
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enum rapl_primitives prim,
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bool xlate, u64 *data);
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static int rapl_write_data_raw(struct rapl_domain *rd,
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enum rapl_primitives prim,
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unsigned long long value);
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static u64 rapl_unit_xlate(struct rapl_domain *rd,
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enum unit_type type, u64 value,
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int to_raw);
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static void package_power_limit_irq_save(struct rapl_package *rp);
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static LIST_HEAD(rapl_packages); /* guarded by CPU hotplug lock */
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static const char * const rapl_domain_names[] = {
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"package",
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"core",
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"uncore",
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"dram",
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"psys",
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};
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static struct powercap_control_type *control_type; /* PowerCap Controller */
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static struct rapl_domain *platform_rapl_domain; /* Platform (PSys) domain */
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/* caller to ensure CPU hotplug lock is held */
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static struct rapl_package *find_package_by_id(int id)
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{
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struct rapl_package *rp;
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list_for_each_entry(rp, &rapl_packages, plist) {
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if (rp->id == id)
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return rp;
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}
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return NULL;
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}
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static int get_energy_counter(struct powercap_zone *power_zone, u64 *energy_raw)
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{
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struct rapl_domain *rd;
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u64 energy_now;
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/* prevent CPU hotplug, make sure the RAPL domain does not go
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* away while reading the counter.
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*/
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get_online_cpus();
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rd = power_zone_to_rapl_domain(power_zone);
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if (!rapl_read_data_raw(rd, ENERGY_COUNTER, true, &energy_now)) {
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*energy_raw = energy_now;
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put_online_cpus();
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return 0;
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}
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put_online_cpus();
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return -EIO;
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}
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static int get_max_energy_counter(struct powercap_zone *pcd_dev, u64 *energy)
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{
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struct rapl_domain *rd = power_zone_to_rapl_domain(pcd_dev);
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*energy = rapl_unit_xlate(rd, ENERGY_UNIT, ENERGY_STATUS_MASK, 0);
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return 0;
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}
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static int release_zone(struct powercap_zone *power_zone)
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{
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struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
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struct rapl_package *rp = rd->rp;
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/* package zone is the last zone of a package, we can free
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* memory here since all children has been unregistered.
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*/
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if (rd->id == RAPL_DOMAIN_PACKAGE) {
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kfree(rd);
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rp->domains = NULL;
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}
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return 0;
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}
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static int find_nr_power_limit(struct rapl_domain *rd)
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{
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int i, nr_pl = 0;
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for (i = 0; i < NR_POWER_LIMITS; i++) {
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if (rd->rpl[i].name)
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nr_pl++;
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}
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return nr_pl;
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}
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static int set_domain_enable(struct powercap_zone *power_zone, bool mode)
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{
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struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
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if (rd->state & DOMAIN_STATE_BIOS_LOCKED)
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return -EACCES;
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get_online_cpus();
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rapl_write_data_raw(rd, PL1_ENABLE, mode);
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if (rapl_defaults->set_floor_freq)
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rapl_defaults->set_floor_freq(rd, mode);
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put_online_cpus();
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return 0;
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}
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static int get_domain_enable(struct powercap_zone *power_zone, bool *mode)
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{
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struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
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u64 val;
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if (rd->state & DOMAIN_STATE_BIOS_LOCKED) {
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*mode = false;
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return 0;
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}
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get_online_cpus();
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if (rapl_read_data_raw(rd, PL1_ENABLE, true, &val)) {
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put_online_cpus();
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return -EIO;
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}
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*mode = val;
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put_online_cpus();
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return 0;
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}
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/* per RAPL domain ops, in the order of rapl_domain_type */
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static const struct powercap_zone_ops zone_ops[] = {
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/* RAPL_DOMAIN_PACKAGE */
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{
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.get_energy_uj = get_energy_counter,
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.get_max_energy_range_uj = get_max_energy_counter,
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.release = release_zone,
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.set_enable = set_domain_enable,
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.get_enable = get_domain_enable,
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},
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/* RAPL_DOMAIN_PP0 */
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{
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.get_energy_uj = get_energy_counter,
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.get_max_energy_range_uj = get_max_energy_counter,
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.release = release_zone,
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.set_enable = set_domain_enable,
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.get_enable = get_domain_enable,
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},
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/* RAPL_DOMAIN_PP1 */
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{
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.get_energy_uj = get_energy_counter,
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.get_max_energy_range_uj = get_max_energy_counter,
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.release = release_zone,
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.set_enable = set_domain_enable,
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.get_enable = get_domain_enable,
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},
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/* RAPL_DOMAIN_DRAM */
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{
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.get_energy_uj = get_energy_counter,
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.get_max_energy_range_uj = get_max_energy_counter,
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.release = release_zone,
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.set_enable = set_domain_enable,
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.get_enable = get_domain_enable,
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},
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/* RAPL_DOMAIN_PLATFORM */
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{
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.get_energy_uj = get_energy_counter,
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.get_max_energy_range_uj = get_max_energy_counter,
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.release = release_zone,
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.set_enable = set_domain_enable,
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.get_enable = get_domain_enable,
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},
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};
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/*
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* Constraint index used by powercap can be different than power limit (PL)
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* index in that some PLs maybe missing due to non-existant MSRs. So we
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* need to convert here by finding the valid PLs only (name populated).
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*/
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static int contraint_to_pl(struct rapl_domain *rd, int cid)
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{
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int i, j;
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for (i = 0, j = 0; i < NR_POWER_LIMITS; i++) {
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if ((rd->rpl[i].name) && j++ == cid) {
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pr_debug("%s: index %d\n", __func__, i);
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return i;
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}
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}
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pr_err("Cannot find matching power limit for constraint %d\n", cid);
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return -EINVAL;
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}
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static int set_power_limit(struct powercap_zone *power_zone, int cid,
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u64 power_limit)
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{
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struct rapl_domain *rd;
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struct rapl_package *rp;
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int ret = 0;
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int id;
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get_online_cpus();
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rd = power_zone_to_rapl_domain(power_zone);
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id = contraint_to_pl(rd, cid);
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if (id < 0) {
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ret = id;
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goto set_exit;
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}
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rp = rd->rp;
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if (rd->state & DOMAIN_STATE_BIOS_LOCKED) {
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dev_warn(&power_zone->dev, "%s locked by BIOS, monitoring only\n",
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rd->name);
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ret = -EACCES;
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goto set_exit;
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}
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switch (rd->rpl[id].prim_id) {
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case PL1_ENABLE:
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rapl_write_data_raw(rd, POWER_LIMIT1, power_limit);
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break;
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case PL2_ENABLE:
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rapl_write_data_raw(rd, POWER_LIMIT2, power_limit);
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break;
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default:
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ret = -EINVAL;
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}
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if (!ret)
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package_power_limit_irq_save(rp);
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set_exit:
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put_online_cpus();
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return ret;
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}
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static int get_current_power_limit(struct powercap_zone *power_zone, int cid,
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u64 *data)
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{
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struct rapl_domain *rd;
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u64 val;
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int prim;
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int ret = 0;
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int id;
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get_online_cpus();
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rd = power_zone_to_rapl_domain(power_zone);
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id = contraint_to_pl(rd, cid);
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if (id < 0) {
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ret = id;
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goto get_exit;
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}
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|
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switch (rd->rpl[id].prim_id) {
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case PL1_ENABLE:
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prim = POWER_LIMIT1;
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break;
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case PL2_ENABLE:
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prim = POWER_LIMIT2;
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break;
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default:
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put_online_cpus();
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return -EINVAL;
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}
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if (rapl_read_data_raw(rd, prim, true, &val))
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|
ret = -EIO;
|
|
else
|
|
*data = val;
|
|
|
|
get_exit:
|
|
put_online_cpus();
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int set_time_window(struct powercap_zone *power_zone, int cid,
|
|
u64 window)
|
|
{
|
|
struct rapl_domain *rd;
|
|
int ret = 0;
|
|
int id;
|
|
|
|
get_online_cpus();
|
|
rd = power_zone_to_rapl_domain(power_zone);
|
|
id = contraint_to_pl(rd, cid);
|
|
if (id < 0) {
|
|
ret = id;
|
|
goto set_time_exit;
|
|
}
|
|
|
|
switch (rd->rpl[id].prim_id) {
|
|
case PL1_ENABLE:
|
|
rapl_write_data_raw(rd, TIME_WINDOW1, window);
|
|
break;
|
|
case PL2_ENABLE:
|
|
rapl_write_data_raw(rd, TIME_WINDOW2, window);
|
|
break;
|
|
default:
|
|
ret = -EINVAL;
|
|
}
|
|
|
|
set_time_exit:
|
|
put_online_cpus();
|
|
return ret;
|
|
}
|
|
|
|
static int get_time_window(struct powercap_zone *power_zone, int cid, u64 *data)
|
|
{
|
|
struct rapl_domain *rd;
|
|
u64 val;
|
|
int ret = 0;
|
|
int id;
|
|
|
|
get_online_cpus();
|
|
rd = power_zone_to_rapl_domain(power_zone);
|
|
id = contraint_to_pl(rd, cid);
|
|
if (id < 0) {
|
|
ret = id;
|
|
goto get_time_exit;
|
|
}
|
|
|
|
switch (rd->rpl[id].prim_id) {
|
|
case PL1_ENABLE:
|
|
ret = rapl_read_data_raw(rd, TIME_WINDOW1, true, &val);
|
|
break;
|
|
case PL2_ENABLE:
|
|
ret = rapl_read_data_raw(rd, TIME_WINDOW2, true, &val);
|
|
break;
|
|
default:
|
|
put_online_cpus();
|
|
return -EINVAL;
|
|
}
|
|
if (!ret)
|
|
*data = val;
|
|
|
|
get_time_exit:
|
|
put_online_cpus();
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const char *get_constraint_name(struct powercap_zone *power_zone, int cid)
|
|
{
|
|
struct rapl_domain *rd;
|
|
int id;
|
|
|
|
rd = power_zone_to_rapl_domain(power_zone);
|
|
id = contraint_to_pl(rd, cid);
|
|
if (id >= 0)
|
|
return rd->rpl[id].name;
|
|
|
|
return NULL;
|
|
}
|
|
|
|
|
|
static int get_max_power(struct powercap_zone *power_zone, int id,
|
|
u64 *data)
|
|
{
|
|
struct rapl_domain *rd;
|
|
u64 val;
|
|
int prim;
|
|
int ret = 0;
|
|
|
|
get_online_cpus();
|
|
rd = power_zone_to_rapl_domain(power_zone);
|
|
switch (rd->rpl[id].prim_id) {
|
|
case PL1_ENABLE:
|
|
prim = THERMAL_SPEC_POWER;
|
|
break;
|
|
case PL2_ENABLE:
|
|
prim = MAX_POWER;
|
|
break;
|
|
default:
|
|
put_online_cpus();
|
|
return -EINVAL;
|
|
}
|
|
if (rapl_read_data_raw(rd, prim, true, &val))
|
|
ret = -EIO;
|
|
else
|
|
*data = val;
|
|
|
|
put_online_cpus();
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct powercap_zone_constraint_ops constraint_ops = {
|
|
.set_power_limit_uw = set_power_limit,
|
|
.get_power_limit_uw = get_current_power_limit,
|
|
.set_time_window_us = set_time_window,
|
|
.get_time_window_us = get_time_window,
|
|
.get_max_power_uw = get_max_power,
|
|
.get_name = get_constraint_name,
|
|
};
|
|
|
|
/* called after domain detection and package level data are set */
|
|
static void rapl_init_domains(struct rapl_package *rp)
|
|
{
|
|
int i;
|
|
struct rapl_domain *rd = rp->domains;
|
|
|
|
for (i = 0; i < RAPL_DOMAIN_MAX; i++) {
|
|
unsigned int mask = rp->domain_map & (1 << i);
|
|
switch (mask) {
|
|
case BIT(RAPL_DOMAIN_PACKAGE):
|
|
rd->name = rapl_domain_names[RAPL_DOMAIN_PACKAGE];
|
|
rd->id = RAPL_DOMAIN_PACKAGE;
|
|
rd->msrs[0] = MSR_PKG_POWER_LIMIT;
|
|
rd->msrs[1] = MSR_PKG_ENERGY_STATUS;
|
|
rd->msrs[2] = MSR_PKG_PERF_STATUS;
|
|
rd->msrs[3] = 0;
|
|
rd->msrs[4] = MSR_PKG_POWER_INFO;
|
|
rd->rpl[0].prim_id = PL1_ENABLE;
|
|
rd->rpl[0].name = pl1_name;
|
|
rd->rpl[1].prim_id = PL2_ENABLE;
|
|
rd->rpl[1].name = pl2_name;
|
|
break;
|
|
case BIT(RAPL_DOMAIN_PP0):
|
|
rd->name = rapl_domain_names[RAPL_DOMAIN_PP0];
|
|
rd->id = RAPL_DOMAIN_PP0;
|
|
rd->msrs[0] = MSR_PP0_POWER_LIMIT;
|
|
rd->msrs[1] = MSR_PP0_ENERGY_STATUS;
|
|
rd->msrs[2] = 0;
|
|
rd->msrs[3] = MSR_PP0_POLICY;
|
|
rd->msrs[4] = 0;
|
|
rd->rpl[0].prim_id = PL1_ENABLE;
|
|
rd->rpl[0].name = pl1_name;
|
|
break;
|
|
case BIT(RAPL_DOMAIN_PP1):
|
|
rd->name = rapl_domain_names[RAPL_DOMAIN_PP1];
|
|
rd->id = RAPL_DOMAIN_PP1;
|
|
rd->msrs[0] = MSR_PP1_POWER_LIMIT;
|
|
rd->msrs[1] = MSR_PP1_ENERGY_STATUS;
|
|
rd->msrs[2] = 0;
|
|
rd->msrs[3] = MSR_PP1_POLICY;
|
|
rd->msrs[4] = 0;
|
|
rd->rpl[0].prim_id = PL1_ENABLE;
|
|
rd->rpl[0].name = pl1_name;
|
|
break;
|
|
case BIT(RAPL_DOMAIN_DRAM):
|
|
rd->name = rapl_domain_names[RAPL_DOMAIN_DRAM];
|
|
rd->id = RAPL_DOMAIN_DRAM;
|
|
rd->msrs[0] = MSR_DRAM_POWER_LIMIT;
|
|
rd->msrs[1] = MSR_DRAM_ENERGY_STATUS;
|
|
rd->msrs[2] = MSR_DRAM_PERF_STATUS;
|
|
rd->msrs[3] = 0;
|
|
rd->msrs[4] = MSR_DRAM_POWER_INFO;
|
|
rd->rpl[0].prim_id = PL1_ENABLE;
|
|
rd->rpl[0].name = pl1_name;
|
|
rd->domain_energy_unit =
|
|
rapl_defaults->dram_domain_energy_unit;
|
|
if (rd->domain_energy_unit)
|
|
pr_info("DRAM domain energy unit %dpj\n",
|
|
rd->domain_energy_unit);
|
|
break;
|
|
}
|
|
if (mask) {
|
|
rd->rp = rp;
|
|
rd++;
|
|
}
|
|
}
|
|
}
|
|
|
|
static u64 rapl_unit_xlate(struct rapl_domain *rd, enum unit_type type,
|
|
u64 value, int to_raw)
|
|
{
|
|
u64 units = 1;
|
|
struct rapl_package *rp = rd->rp;
|
|
u64 scale = 1;
|
|
|
|
switch (type) {
|
|
case POWER_UNIT:
|
|
units = rp->power_unit;
|
|
break;
|
|
case ENERGY_UNIT:
|
|
scale = ENERGY_UNIT_SCALE;
|
|
/* per domain unit takes precedence */
|
|
if (rd->domain_energy_unit)
|
|
units = rd->domain_energy_unit;
|
|
else
|
|
units = rp->energy_unit;
|
|
break;
|
|
case TIME_UNIT:
|
|
return rapl_defaults->compute_time_window(rp, value, to_raw);
|
|
case ARBITRARY_UNIT:
|
|
default:
|
|
return value;
|
|
};
|
|
|
|
if (to_raw)
|
|
return div64_u64(value, units) * scale;
|
|
|
|
value *= units;
|
|
|
|
return div64_u64(value, scale);
|
|
}
|
|
|
|
/* in the order of enum rapl_primitives */
|
|
static struct rapl_primitive_info rpi[] = {
|
|
/* name, mask, shift, msr index, unit divisor */
|
|
PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0,
|
|
RAPL_DOMAIN_MSR_STATUS, ENERGY_UNIT, 0),
|
|
PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0,
|
|
RAPL_DOMAIN_MSR_LIMIT, POWER_UNIT, 0),
|
|
PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32,
|
|
RAPL_DOMAIN_MSR_LIMIT, POWER_UNIT, 0),
|
|
PRIMITIVE_INFO_INIT(FW_LOCK, POWER_PP_LOCK, 31,
|
|
RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
|
|
PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15,
|
|
RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
|
|
PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16,
|
|
RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
|
|
PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47,
|
|
RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
|
|
PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48,
|
|
RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
|
|
PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17,
|
|
RAPL_DOMAIN_MSR_LIMIT, TIME_UNIT, 0),
|
|
PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49,
|
|
RAPL_DOMAIN_MSR_LIMIT, TIME_UNIT, 0),
|
|
PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, POWER_INFO_THERMAL_SPEC_MASK,
|
|
0, RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0),
|
|
PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32,
|
|
RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0),
|
|
PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16,
|
|
RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0),
|
|
PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, POWER_INFO_MAX_TIME_WIN_MASK, 48,
|
|
RAPL_DOMAIN_MSR_INFO, TIME_UNIT, 0),
|
|
PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK, 0,
|
|
RAPL_DOMAIN_MSR_PERF, TIME_UNIT, 0),
|
|
PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0,
|
|
RAPL_DOMAIN_MSR_POLICY, ARBITRARY_UNIT, 0),
|
|
/* non-hardware */
|
|
PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, POWER_UNIT,
|
|
RAPL_PRIMITIVE_DERIVED),
|
|
{NULL, 0, 0, 0},
|
|
};
|
|
|
|
/* Read primitive data based on its related struct rapl_primitive_info.
|
|
* if xlate flag is set, return translated data based on data units, i.e.
|
|
* time, energy, and power.
|
|
* RAPL MSRs are non-architectual and are laid out not consistently across
|
|
* domains. Here we use primitive info to allow writing consolidated access
|
|
* functions.
|
|
* For a given primitive, it is processed by MSR mask and shift. Unit conversion
|
|
* is pre-assigned based on RAPL unit MSRs read at init time.
|
|
* 63-------------------------- 31--------------------------- 0
|
|
* | xxxxx (mask) |
|
|
* | |<- shift ----------------|
|
|
* 63-------------------------- 31--------------------------- 0
|
|
*/
|
|
static int rapl_read_data_raw(struct rapl_domain *rd,
|
|
enum rapl_primitives prim,
|
|
bool xlate, u64 *data)
|
|
{
|
|
u64 value, final;
|
|
u32 msr;
|
|
struct rapl_primitive_info *rp = &rpi[prim];
|
|
int cpu;
|
|
|
|
if (!rp->name || rp->flag & RAPL_PRIMITIVE_DUMMY)
|
|
return -EINVAL;
|
|
|
|
msr = rd->msrs[rp->id];
|
|
if (!msr)
|
|
return -EINVAL;
|
|
|
|
cpu = rd->rp->lead_cpu;
|
|
|
|
/* special-case package domain, which uses a different bit*/
|
|
if (prim == FW_LOCK && rd->id == RAPL_DOMAIN_PACKAGE) {
|
|
rp->mask = POWER_PACKAGE_LOCK;
|
|
rp->shift = 63;
|
|
}
|
|
/* non-hardware data are collected by the polling thread */
|
|
if (rp->flag & RAPL_PRIMITIVE_DERIVED) {
|
|
*data = rd->rdd.primitives[prim];
|
|
return 0;
|
|
}
|
|
|
|
if (rdmsrl_safe_on_cpu(cpu, msr, &value)) {
|
|
pr_debug("failed to read msr 0x%x on cpu %d\n", msr, cpu);
|
|
return -EIO;
|
|
}
|
|
|
|
final = value & rp->mask;
|
|
final = final >> rp->shift;
|
|
if (xlate)
|
|
*data = rapl_unit_xlate(rd, rp->unit, final, 0);
|
|
else
|
|
*data = final;
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
static int msrl_update_safe(u32 msr_no, u64 clear_mask, u64 set_mask)
|
|
{
|
|
int err;
|
|
u64 val;
|
|
|
|
err = rdmsrl_safe(msr_no, &val);
|
|
if (err)
|
|
goto out;
|
|
|
|
val &= ~clear_mask;
|
|
val |= set_mask;
|
|
|
|
err = wrmsrl_safe(msr_no, val);
|
|
|
|
out:
|
|
return err;
|
|
}
|
|
|
|
static void msrl_update_func(void *info)
|
|
{
|
|
struct msrl_action *ma = info;
|
|
|
|
ma->err = msrl_update_safe(ma->msr_no, ma->clear_mask, ma->set_mask);
|
|
}
|
|
|
|
/* Similar use of primitive info in the read counterpart */
|
|
static int rapl_write_data_raw(struct rapl_domain *rd,
|
|
enum rapl_primitives prim,
|
|
unsigned long long value)
|
|
{
|
|
struct rapl_primitive_info *rp = &rpi[prim];
|
|
int cpu;
|
|
u64 bits;
|
|
struct msrl_action ma;
|
|
int ret;
|
|
|
|
cpu = rd->rp->lead_cpu;
|
|
bits = rapl_unit_xlate(rd, rp->unit, value, 1);
|
|
bits <<= rp->shift;
|
|
bits &= rp->mask;
|
|
|
|
memset(&ma, 0, sizeof(ma));
|
|
|
|
ma.msr_no = rd->msrs[rp->id];
|
|
ma.clear_mask = rp->mask;
|
|
ma.set_mask = bits;
|
|
|
|
ret = smp_call_function_single(cpu, msrl_update_func, &ma, 1);
|
|
if (ret)
|
|
WARN_ON_ONCE(ret);
|
|
else
|
|
ret = ma.err;
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Raw RAPL data stored in MSRs are in certain scales. We need to
|
|
* convert them into standard units based on the units reported in
|
|
* the RAPL unit MSRs. This is specific to CPUs as the method to
|
|
* calculate units differ on different CPUs.
|
|
* We convert the units to below format based on CPUs.
|
|
* i.e.
|
|
* energy unit: picoJoules : Represented in picoJoules by default
|
|
* power unit : microWatts : Represented in milliWatts by default
|
|
* time unit : microseconds: Represented in seconds by default
|
|
*/
|
|
static int rapl_check_unit_core(struct rapl_package *rp, int cpu)
|
|
{
|
|
u64 msr_val;
|
|
u32 value;
|
|
|
|
if (rdmsrl_safe_on_cpu(cpu, MSR_RAPL_POWER_UNIT, &msr_val)) {
|
|
pr_err("Failed to read power unit MSR 0x%x on CPU %d, exit.\n",
|
|
MSR_RAPL_POWER_UNIT, cpu);
|
|
return -ENODEV;
|
|
}
|
|
|
|
value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
|
|
rp->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << value);
|
|
|
|
value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
|
|
rp->power_unit = 1000000 / (1 << value);
|
|
|
|
value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
|
|
rp->time_unit = 1000000 / (1 << value);
|
|
|
|
pr_debug("Core CPU package %d energy=%dpJ, time=%dus, power=%duW\n",
|
|
rp->id, rp->energy_unit, rp->time_unit, rp->power_unit);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rapl_check_unit_atom(struct rapl_package *rp, int cpu)
|
|
{
|
|
u64 msr_val;
|
|
u32 value;
|
|
|
|
if (rdmsrl_safe_on_cpu(cpu, MSR_RAPL_POWER_UNIT, &msr_val)) {
|
|
pr_err("Failed to read power unit MSR 0x%x on CPU %d, exit.\n",
|
|
MSR_RAPL_POWER_UNIT, cpu);
|
|
return -ENODEV;
|
|
}
|
|
value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
|
|
rp->energy_unit = ENERGY_UNIT_SCALE * 1 << value;
|
|
|
|
value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
|
|
rp->power_unit = (1 << value) * 1000;
|
|
|
|
value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
|
|
rp->time_unit = 1000000 / (1 << value);
|
|
|
|
pr_debug("Atom package %d energy=%dpJ, time=%dus, power=%duW\n",
|
|
rp->id, rp->energy_unit, rp->time_unit, rp->power_unit);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void power_limit_irq_save_cpu(void *info)
|
|
{
|
|
u32 l, h = 0;
|
|
struct rapl_package *rp = (struct rapl_package *)info;
|
|
|
|
/* save the state of PLN irq mask bit before disabling it */
|
|
rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h);
|
|
if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED)) {
|
|
rp->power_limit_irq = l & PACKAGE_THERM_INT_PLN_ENABLE;
|
|
rp->power_limit_irq |= PACKAGE_PLN_INT_SAVED;
|
|
}
|
|
l &= ~PACKAGE_THERM_INT_PLN_ENABLE;
|
|
wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
|
|
}
|
|
|
|
|
|
/* REVISIT:
|
|
* When package power limit is set artificially low by RAPL, LVT
|
|
* thermal interrupt for package power limit should be ignored
|
|
* since we are not really exceeding the real limit. The intention
|
|
* is to avoid excessive interrupts while we are trying to save power.
|
|
* A useful feature might be routing the package_power_limit interrupt
|
|
* to userspace via eventfd. once we have a usecase, this is simple
|
|
* to do by adding an atomic notifier.
|
|
*/
|
|
|
|
static void package_power_limit_irq_save(struct rapl_package *rp)
|
|
{
|
|
if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN))
|
|
return;
|
|
|
|
smp_call_function_single(rp->lead_cpu, power_limit_irq_save_cpu, rp, 1);
|
|
}
|
|
|
|
/*
|
|
* Restore per package power limit interrupt enable state. Called from cpu
|
|
* hotplug code on package removal.
|
|
*/
|
|
static void package_power_limit_irq_restore(struct rapl_package *rp)
|
|
{
|
|
u32 l, h;
|
|
|
|
if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN))
|
|
return;
|
|
|
|
/* irq enable state not saved, nothing to restore */
|
|
if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED))
|
|
return;
|
|
|
|
rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h);
|
|
|
|
if (rp->power_limit_irq & PACKAGE_THERM_INT_PLN_ENABLE)
|
|
l |= PACKAGE_THERM_INT_PLN_ENABLE;
|
|
else
|
|
l &= ~PACKAGE_THERM_INT_PLN_ENABLE;
|
|
|
|
wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
|
|
}
|
|
|
|
static void set_floor_freq_default(struct rapl_domain *rd, bool mode)
|
|
{
|
|
int nr_powerlimit = find_nr_power_limit(rd);
|
|
|
|
/* always enable clamp such that p-state can go below OS requested
|
|
* range. power capping priority over guranteed frequency.
|
|
*/
|
|
rapl_write_data_raw(rd, PL1_CLAMP, mode);
|
|
|
|
/* some domains have pl2 */
|
|
if (nr_powerlimit > 1) {
|
|
rapl_write_data_raw(rd, PL2_ENABLE, mode);
|
|
rapl_write_data_raw(rd, PL2_CLAMP, mode);
|
|
}
|
|
}
|
|
|
|
static void set_floor_freq_atom(struct rapl_domain *rd, bool enable)
|
|
{
|
|
static u32 power_ctrl_orig_val;
|
|
u32 mdata;
|
|
|
|
if (!rapl_defaults->floor_freq_reg_addr) {
|
|
pr_err("Invalid floor frequency config register\n");
|
|
return;
|
|
}
|
|
|
|
if (!power_ctrl_orig_val)
|
|
iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_CR_READ,
|
|
rapl_defaults->floor_freq_reg_addr,
|
|
&power_ctrl_orig_val);
|
|
mdata = power_ctrl_orig_val;
|
|
if (enable) {
|
|
mdata &= ~(0x7f << 8);
|
|
mdata |= 1 << 8;
|
|
}
|
|
iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_CR_WRITE,
|
|
rapl_defaults->floor_freq_reg_addr, mdata);
|
|
}
|
|
|
|
static u64 rapl_compute_time_window_core(struct rapl_package *rp, u64 value,
|
|
bool to_raw)
|
|
{
|
|
u64 f, y; /* fraction and exp. used for time unit */
|
|
|
|
/*
|
|
* Special processing based on 2^Y*(1+F/4), refer
|
|
* to Intel Software Developer's manual Vol.3B: CH 14.9.3.
|
|
*/
|
|
if (!to_raw) {
|
|
f = (value & 0x60) >> 5;
|
|
y = value & 0x1f;
|
|
value = (1 << y) * (4 + f) * rp->time_unit / 4;
|
|
} else {
|
|
do_div(value, rp->time_unit);
|
|
y = ilog2(value);
|
|
f = div64_u64(4 * (value - (1 << y)), 1 << y);
|
|
value = (y & 0x1f) | ((f & 0x3) << 5);
|
|
}
|
|
return value;
|
|
}
|
|
|
|
static u64 rapl_compute_time_window_atom(struct rapl_package *rp, u64 value,
|
|
bool to_raw)
|
|
{
|
|
/*
|
|
* Atom time unit encoding is straight forward val * time_unit,
|
|
* where time_unit is default to 1 sec. Never 0.
|
|
*/
|
|
if (!to_raw)
|
|
return (value) ? value *= rp->time_unit : rp->time_unit;
|
|
else
|
|
value = div64_u64(value, rp->time_unit);
|
|
|
|
return value;
|
|
}
|
|
|
|
static const struct rapl_defaults rapl_defaults_core = {
|
|
.floor_freq_reg_addr = 0,
|
|
.check_unit = rapl_check_unit_core,
|
|
.set_floor_freq = set_floor_freq_default,
|
|
.compute_time_window = rapl_compute_time_window_core,
|
|
};
|
|
|
|
static const struct rapl_defaults rapl_defaults_hsw_server = {
|
|
.check_unit = rapl_check_unit_core,
|
|
.set_floor_freq = set_floor_freq_default,
|
|
.compute_time_window = rapl_compute_time_window_core,
|
|
.dram_domain_energy_unit = 15300,
|
|
};
|
|
|
|
static const struct rapl_defaults rapl_defaults_byt = {
|
|
.floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_BYT,
|
|
.check_unit = rapl_check_unit_atom,
|
|
.set_floor_freq = set_floor_freq_atom,
|
|
.compute_time_window = rapl_compute_time_window_atom,
|
|
};
|
|
|
|
static const struct rapl_defaults rapl_defaults_tng = {
|
|
.floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_TNG,
|
|
.check_unit = rapl_check_unit_atom,
|
|
.set_floor_freq = set_floor_freq_atom,
|
|
.compute_time_window = rapl_compute_time_window_atom,
|
|
};
|
|
|
|
static const struct rapl_defaults rapl_defaults_ann = {
|
|
.floor_freq_reg_addr = 0,
|
|
.check_unit = rapl_check_unit_atom,
|
|
.set_floor_freq = NULL,
|
|
.compute_time_window = rapl_compute_time_window_atom,
|
|
};
|
|
|
|
static const struct rapl_defaults rapl_defaults_cht = {
|
|
.floor_freq_reg_addr = 0,
|
|
.check_unit = rapl_check_unit_atom,
|
|
.set_floor_freq = NULL,
|
|
.compute_time_window = rapl_compute_time_window_atom,
|
|
};
|
|
|
|
#define RAPL_CPU(_model, _ops) { \
|
|
.vendor = X86_VENDOR_INTEL, \
|
|
.family = 6, \
|
|
.model = _model, \
|
|
.driver_data = (kernel_ulong_t)&_ops, \
|
|
}
|
|
|
|
static const struct x86_cpu_id rapl_ids[] __initconst = {
|
|
RAPL_CPU(INTEL_FAM6_SANDYBRIDGE, rapl_defaults_core),
|
|
RAPL_CPU(INTEL_FAM6_SANDYBRIDGE_X, rapl_defaults_core),
|
|
|
|
RAPL_CPU(INTEL_FAM6_IVYBRIDGE, rapl_defaults_core),
|
|
RAPL_CPU(INTEL_FAM6_IVYBRIDGE_X, rapl_defaults_core),
|
|
|
|
RAPL_CPU(INTEL_FAM6_HASWELL_CORE, rapl_defaults_core),
|
|
RAPL_CPU(INTEL_FAM6_HASWELL_ULT, rapl_defaults_core),
|
|
RAPL_CPU(INTEL_FAM6_HASWELL_GT3E, rapl_defaults_core),
|
|
RAPL_CPU(INTEL_FAM6_HASWELL_X, rapl_defaults_hsw_server),
|
|
|
|
RAPL_CPU(INTEL_FAM6_BROADWELL_CORE, rapl_defaults_core),
|
|
RAPL_CPU(INTEL_FAM6_BROADWELL_GT3E, rapl_defaults_core),
|
|
RAPL_CPU(INTEL_FAM6_BROADWELL_XEON_D, rapl_defaults_core),
|
|
RAPL_CPU(INTEL_FAM6_BROADWELL_X, rapl_defaults_hsw_server),
|
|
|
|
RAPL_CPU(INTEL_FAM6_SKYLAKE_DESKTOP, rapl_defaults_core),
|
|
RAPL_CPU(INTEL_FAM6_SKYLAKE_MOBILE, rapl_defaults_core),
|
|
RAPL_CPU(INTEL_FAM6_SKYLAKE_X, rapl_defaults_hsw_server),
|
|
RAPL_CPU(INTEL_FAM6_KABYLAKE_MOBILE, rapl_defaults_core),
|
|
RAPL_CPU(INTEL_FAM6_KABYLAKE_DESKTOP, rapl_defaults_core),
|
|
RAPL_CPU(INTEL_FAM6_CANNONLAKE_MOBILE, rapl_defaults_core),
|
|
|
|
RAPL_CPU(INTEL_FAM6_ATOM_SILVERMONT1, rapl_defaults_byt),
|
|
RAPL_CPU(INTEL_FAM6_ATOM_AIRMONT, rapl_defaults_cht),
|
|
RAPL_CPU(INTEL_FAM6_ATOM_MERRIFIELD, rapl_defaults_tng),
|
|
RAPL_CPU(INTEL_FAM6_ATOM_MOOREFIELD, rapl_defaults_ann),
|
|
RAPL_CPU(INTEL_FAM6_ATOM_GOLDMONT, rapl_defaults_core),
|
|
RAPL_CPU(INTEL_FAM6_ATOM_GEMINI_LAKE, rapl_defaults_core),
|
|
RAPL_CPU(INTEL_FAM6_ATOM_DENVERTON, rapl_defaults_core),
|
|
|
|
RAPL_CPU(INTEL_FAM6_XEON_PHI_KNL, rapl_defaults_hsw_server),
|
|
RAPL_CPU(INTEL_FAM6_XEON_PHI_KNM, rapl_defaults_hsw_server),
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(x86cpu, rapl_ids);
|
|
|
|
/* Read once for all raw primitive data for domains */
|
|
static void rapl_update_domain_data(struct rapl_package *rp)
|
|
{
|
|
int dmn, prim;
|
|
u64 val;
|
|
|
|
for (dmn = 0; dmn < rp->nr_domains; dmn++) {
|
|
pr_debug("update package %d domain %s data\n", rp->id,
|
|
rp->domains[dmn].name);
|
|
/* exclude non-raw primitives */
|
|
for (prim = 0; prim < NR_RAW_PRIMITIVES; prim++) {
|
|
if (!rapl_read_data_raw(&rp->domains[dmn], prim,
|
|
rpi[prim].unit, &val))
|
|
rp->domains[dmn].rdd.primitives[prim] = val;
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
static void rapl_unregister_powercap(void)
|
|
{
|
|
if (platform_rapl_domain) {
|
|
powercap_unregister_zone(control_type,
|
|
&platform_rapl_domain->power_zone);
|
|
kfree(platform_rapl_domain);
|
|
}
|
|
powercap_unregister_control_type(control_type);
|
|
}
|
|
|
|
static int rapl_package_register_powercap(struct rapl_package *rp)
|
|
{
|
|
struct rapl_domain *rd;
|
|
char dev_name[17]; /* max domain name = 7 + 1 + 8 for int + 1 for null*/
|
|
struct powercap_zone *power_zone = NULL;
|
|
int nr_pl, ret;
|
|
|
|
/* Update the domain data of the new package */
|
|
rapl_update_domain_data(rp);
|
|
|
|
/* first we register package domain as the parent zone*/
|
|
for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
|
|
if (rd->id == RAPL_DOMAIN_PACKAGE) {
|
|
nr_pl = find_nr_power_limit(rd);
|
|
pr_debug("register socket %d package domain %s\n",
|
|
rp->id, rd->name);
|
|
memset(dev_name, 0, sizeof(dev_name));
|
|
snprintf(dev_name, sizeof(dev_name), "%s-%d",
|
|
rd->name, rp->id);
|
|
power_zone = powercap_register_zone(&rd->power_zone,
|
|
control_type,
|
|
dev_name, NULL,
|
|
&zone_ops[rd->id],
|
|
nr_pl,
|
|
&constraint_ops);
|
|
if (IS_ERR(power_zone)) {
|
|
pr_debug("failed to register package, %d\n",
|
|
rp->id);
|
|
return PTR_ERR(power_zone);
|
|
}
|
|
/* track parent zone in per package/socket data */
|
|
rp->power_zone = power_zone;
|
|
/* done, only one package domain per socket */
|
|
break;
|
|
}
|
|
}
|
|
if (!power_zone) {
|
|
pr_err("no package domain found, unknown topology!\n");
|
|
return -ENODEV;
|
|
}
|
|
/* now register domains as children of the socket/package*/
|
|
for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
|
|
if (rd->id == RAPL_DOMAIN_PACKAGE)
|
|
continue;
|
|
/* number of power limits per domain varies */
|
|
nr_pl = find_nr_power_limit(rd);
|
|
power_zone = powercap_register_zone(&rd->power_zone,
|
|
control_type, rd->name,
|
|
rp->power_zone,
|
|
&zone_ops[rd->id], nr_pl,
|
|
&constraint_ops);
|
|
|
|
if (IS_ERR(power_zone)) {
|
|
pr_debug("failed to register power_zone, %d:%s:%s\n",
|
|
rp->id, rd->name, dev_name);
|
|
ret = PTR_ERR(power_zone);
|
|
goto err_cleanup;
|
|
}
|
|
}
|
|
return 0;
|
|
|
|
err_cleanup:
|
|
/*
|
|
* Clean up previously initialized domains within the package if we
|
|
* failed after the first domain setup.
|
|
*/
|
|
while (--rd >= rp->domains) {
|
|
pr_debug("unregister package %d domain %s\n", rp->id, rd->name);
|
|
powercap_unregister_zone(control_type, &rd->power_zone);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int __init rapl_register_psys(void)
|
|
{
|
|
struct rapl_domain *rd;
|
|
struct powercap_zone *power_zone;
|
|
u64 val;
|
|
|
|
if (rdmsrl_safe_on_cpu(0, MSR_PLATFORM_ENERGY_STATUS, &val) || !val)
|
|
return -ENODEV;
|
|
|
|
if (rdmsrl_safe_on_cpu(0, MSR_PLATFORM_POWER_LIMIT, &val) || !val)
|
|
return -ENODEV;
|
|
|
|
rd = kzalloc(sizeof(*rd), GFP_KERNEL);
|
|
if (!rd)
|
|
return -ENOMEM;
|
|
|
|
rd->name = rapl_domain_names[RAPL_DOMAIN_PLATFORM];
|
|
rd->id = RAPL_DOMAIN_PLATFORM;
|
|
rd->msrs[0] = MSR_PLATFORM_POWER_LIMIT;
|
|
rd->msrs[1] = MSR_PLATFORM_ENERGY_STATUS;
|
|
rd->rpl[0].prim_id = PL1_ENABLE;
|
|
rd->rpl[0].name = pl1_name;
|
|
rd->rpl[1].prim_id = PL2_ENABLE;
|
|
rd->rpl[1].name = pl2_name;
|
|
rd->rp = find_package_by_id(0);
|
|
|
|
power_zone = powercap_register_zone(&rd->power_zone, control_type,
|
|
"psys", NULL,
|
|
&zone_ops[RAPL_DOMAIN_PLATFORM],
|
|
2, &constraint_ops);
|
|
|
|
if (IS_ERR(power_zone)) {
|
|
kfree(rd);
|
|
return PTR_ERR(power_zone);
|
|
}
|
|
|
|
platform_rapl_domain = rd;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __init rapl_register_powercap(void)
|
|
{
|
|
control_type = powercap_register_control_type(NULL, "intel-rapl", NULL);
|
|
if (IS_ERR(control_type)) {
|
|
pr_debug("failed to register powercap control_type.\n");
|
|
return PTR_ERR(control_type);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int rapl_check_domain(int cpu, int domain)
|
|
{
|
|
unsigned msr;
|
|
u64 val = 0;
|
|
|
|
switch (domain) {
|
|
case RAPL_DOMAIN_PACKAGE:
|
|
msr = MSR_PKG_ENERGY_STATUS;
|
|
break;
|
|
case RAPL_DOMAIN_PP0:
|
|
msr = MSR_PP0_ENERGY_STATUS;
|
|
break;
|
|
case RAPL_DOMAIN_PP1:
|
|
msr = MSR_PP1_ENERGY_STATUS;
|
|
break;
|
|
case RAPL_DOMAIN_DRAM:
|
|
msr = MSR_DRAM_ENERGY_STATUS;
|
|
break;
|
|
case RAPL_DOMAIN_PLATFORM:
|
|
/* PSYS(PLATFORM) is not a CPU domain, so avoid printng error */
|
|
return -EINVAL;
|
|
default:
|
|
pr_err("invalid domain id %d\n", domain);
|
|
return -EINVAL;
|
|
}
|
|
/* make sure domain counters are available and contains non-zero
|
|
* values, otherwise skip it.
|
|
*/
|
|
if (rdmsrl_safe_on_cpu(cpu, msr, &val) || !val)
|
|
return -ENODEV;
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
* Check if power limits are available. Two cases when they are not available:
|
|
* 1. Locked by BIOS, in this case we still provide read-only access so that
|
|
* users can see what limit is set by the BIOS.
|
|
* 2. Some CPUs make some domains monitoring only which means PLx MSRs may not
|
|
* exist at all. In this case, we do not show the contraints in powercap.
|
|
*
|
|
* Called after domains are detected and initialized.
|
|
*/
|
|
static void rapl_detect_powerlimit(struct rapl_domain *rd)
|
|
{
|
|
u64 val64;
|
|
int i;
|
|
|
|
/* check if the domain is locked by BIOS, ignore if MSR doesn't exist */
|
|
if (!rapl_read_data_raw(rd, FW_LOCK, false, &val64)) {
|
|
if (val64) {
|
|
pr_info("RAPL package %d domain %s locked by BIOS\n",
|
|
rd->rp->id, rd->name);
|
|
rd->state |= DOMAIN_STATE_BIOS_LOCKED;
|
|
}
|
|
}
|
|
/* check if power limit MSRs exists, otherwise domain is monitoring only */
|
|
for (i = 0; i < NR_POWER_LIMITS; i++) {
|
|
int prim = rd->rpl[i].prim_id;
|
|
if (rapl_read_data_raw(rd, prim, false, &val64))
|
|
rd->rpl[i].name = NULL;
|
|
}
|
|
}
|
|
|
|
/* Detect active and valid domains for the given CPU, caller must
|
|
* ensure the CPU belongs to the targeted package and CPU hotlug is disabled.
|
|
*/
|
|
static int rapl_detect_domains(struct rapl_package *rp, int cpu)
|
|
{
|
|
struct rapl_domain *rd;
|
|
int i;
|
|
|
|
for (i = 0; i < RAPL_DOMAIN_MAX; i++) {
|
|
/* use physical package id to read counters */
|
|
if (!rapl_check_domain(cpu, i)) {
|
|
rp->domain_map |= 1 << i;
|
|
pr_info("Found RAPL domain %s\n", rapl_domain_names[i]);
|
|
}
|
|
}
|
|
rp->nr_domains = bitmap_weight(&rp->domain_map, RAPL_DOMAIN_MAX);
|
|
if (!rp->nr_domains) {
|
|
pr_debug("no valid rapl domains found in package %d\n", rp->id);
|
|
return -ENODEV;
|
|
}
|
|
pr_debug("found %d domains on package %d\n", rp->nr_domains, rp->id);
|
|
|
|
rp->domains = kcalloc(rp->nr_domains + 1, sizeof(struct rapl_domain),
|
|
GFP_KERNEL);
|
|
if (!rp->domains)
|
|
return -ENOMEM;
|
|
|
|
rapl_init_domains(rp);
|
|
|
|
for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++)
|
|
rapl_detect_powerlimit(rd);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* called from CPU hotplug notifier, hotplug lock held */
|
|
static void rapl_remove_package(struct rapl_package *rp)
|
|
{
|
|
struct rapl_domain *rd, *rd_package = NULL;
|
|
|
|
package_power_limit_irq_restore(rp);
|
|
|
|
for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
|
|
rapl_write_data_raw(rd, PL1_ENABLE, 0);
|
|
rapl_write_data_raw(rd, PL1_CLAMP, 0);
|
|
if (find_nr_power_limit(rd) > 1) {
|
|
rapl_write_data_raw(rd, PL2_ENABLE, 0);
|
|
rapl_write_data_raw(rd, PL2_CLAMP, 0);
|
|
}
|
|
if (rd->id == RAPL_DOMAIN_PACKAGE) {
|
|
rd_package = rd;
|
|
continue;
|
|
}
|
|
pr_debug("remove package, undo power limit on %d: %s\n",
|
|
rp->id, rd->name);
|
|
powercap_unregister_zone(control_type, &rd->power_zone);
|
|
}
|
|
/* do parent zone last */
|
|
powercap_unregister_zone(control_type, &rd_package->power_zone);
|
|
list_del(&rp->plist);
|
|
kfree(rp);
|
|
}
|
|
|
|
/* called from CPU hotplug notifier, hotplug lock held */
|
|
static struct rapl_package *rapl_add_package(int cpu, int pkgid)
|
|
{
|
|
struct rapl_package *rp;
|
|
int ret;
|
|
|
|
rp = kzalloc(sizeof(struct rapl_package), GFP_KERNEL);
|
|
if (!rp)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
/* add the new package to the list */
|
|
rp->id = pkgid;
|
|
rp->lead_cpu = cpu;
|
|
|
|
/* check if the package contains valid domains */
|
|
if (rapl_detect_domains(rp, cpu) ||
|
|
rapl_defaults->check_unit(rp, cpu)) {
|
|
ret = -ENODEV;
|
|
goto err_free_package;
|
|
}
|
|
ret = rapl_package_register_powercap(rp);
|
|
if (!ret) {
|
|
INIT_LIST_HEAD(&rp->plist);
|
|
list_add(&rp->plist, &rapl_packages);
|
|
return rp;
|
|
}
|
|
|
|
err_free_package:
|
|
kfree(rp->domains);
|
|
kfree(rp);
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
/* Handles CPU hotplug on multi-socket systems.
|
|
* If a CPU goes online as the first CPU of the physical package
|
|
* we add the RAPL package to the system. Similarly, when the last
|
|
* CPU of the package is removed, we remove the RAPL package and its
|
|
* associated domains. Cooling devices are handled accordingly at
|
|
* per-domain level.
|
|
*/
|
|
static int rapl_cpu_online(unsigned int cpu)
|
|
{
|
|
int pkgid = topology_physical_package_id(cpu);
|
|
struct rapl_package *rp;
|
|
|
|
rp = find_package_by_id(pkgid);
|
|
if (!rp) {
|
|
rp = rapl_add_package(cpu, pkgid);
|
|
if (IS_ERR(rp))
|
|
return PTR_ERR(rp);
|
|
}
|
|
cpumask_set_cpu(cpu, &rp->cpumask);
|
|
return 0;
|
|
}
|
|
|
|
static int rapl_cpu_down_prep(unsigned int cpu)
|
|
{
|
|
int pkgid = topology_physical_package_id(cpu);
|
|
struct rapl_package *rp;
|
|
int lead_cpu;
|
|
|
|
rp = find_package_by_id(pkgid);
|
|
if (!rp)
|
|
return 0;
|
|
|
|
cpumask_clear_cpu(cpu, &rp->cpumask);
|
|
lead_cpu = cpumask_first(&rp->cpumask);
|
|
if (lead_cpu >= nr_cpu_ids)
|
|
rapl_remove_package(rp);
|
|
else if (rp->lead_cpu == cpu)
|
|
rp->lead_cpu = lead_cpu;
|
|
return 0;
|
|
}
|
|
|
|
static enum cpuhp_state pcap_rapl_online;
|
|
|
|
static void power_limit_state_save(void)
|
|
{
|
|
struct rapl_package *rp;
|
|
struct rapl_domain *rd;
|
|
int nr_pl, ret, i;
|
|
|
|
get_online_cpus();
|
|
list_for_each_entry(rp, &rapl_packages, plist) {
|
|
if (!rp->power_zone)
|
|
continue;
|
|
rd = power_zone_to_rapl_domain(rp->power_zone);
|
|
nr_pl = find_nr_power_limit(rd);
|
|
for (i = 0; i < nr_pl; i++) {
|
|
switch (rd->rpl[i].prim_id) {
|
|
case PL1_ENABLE:
|
|
ret = rapl_read_data_raw(rd,
|
|
POWER_LIMIT1,
|
|
true,
|
|
&rd->rpl[i].last_power_limit);
|
|
if (ret)
|
|
rd->rpl[i].last_power_limit = 0;
|
|
break;
|
|
case PL2_ENABLE:
|
|
ret = rapl_read_data_raw(rd,
|
|
POWER_LIMIT2,
|
|
true,
|
|
&rd->rpl[i].last_power_limit);
|
|
if (ret)
|
|
rd->rpl[i].last_power_limit = 0;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
put_online_cpus();
|
|
}
|
|
|
|
static void power_limit_state_restore(void)
|
|
{
|
|
struct rapl_package *rp;
|
|
struct rapl_domain *rd;
|
|
int nr_pl, i;
|
|
|
|
get_online_cpus();
|
|
list_for_each_entry(rp, &rapl_packages, plist) {
|
|
if (!rp->power_zone)
|
|
continue;
|
|
rd = power_zone_to_rapl_domain(rp->power_zone);
|
|
nr_pl = find_nr_power_limit(rd);
|
|
for (i = 0; i < nr_pl; i++) {
|
|
switch (rd->rpl[i].prim_id) {
|
|
case PL1_ENABLE:
|
|
if (rd->rpl[i].last_power_limit)
|
|
rapl_write_data_raw(rd,
|
|
POWER_LIMIT1,
|
|
rd->rpl[i].last_power_limit);
|
|
break;
|
|
case PL2_ENABLE:
|
|
if (rd->rpl[i].last_power_limit)
|
|
rapl_write_data_raw(rd,
|
|
POWER_LIMIT2,
|
|
rd->rpl[i].last_power_limit);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
put_online_cpus();
|
|
}
|
|
|
|
static int rapl_pm_callback(struct notifier_block *nb,
|
|
unsigned long mode, void *_unused)
|
|
{
|
|
switch (mode) {
|
|
case PM_SUSPEND_PREPARE:
|
|
power_limit_state_save();
|
|
break;
|
|
case PM_POST_SUSPEND:
|
|
power_limit_state_restore();
|
|
break;
|
|
}
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
static struct notifier_block rapl_pm_notifier = {
|
|
.notifier_call = rapl_pm_callback,
|
|
};
|
|
|
|
static int __init rapl_init(void)
|
|
{
|
|
const struct x86_cpu_id *id;
|
|
int ret;
|
|
|
|
id = x86_match_cpu(rapl_ids);
|
|
if (!id) {
|
|
pr_err("driver does not support CPU family %d model %d\n",
|
|
boot_cpu_data.x86, boot_cpu_data.x86_model);
|
|
|
|
return -ENODEV;
|
|
}
|
|
|
|
rapl_defaults = (struct rapl_defaults *)id->driver_data;
|
|
|
|
ret = rapl_register_powercap();
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powercap/rapl:online",
|
|
rapl_cpu_online, rapl_cpu_down_prep);
|
|
if (ret < 0)
|
|
goto err_unreg;
|
|
pcap_rapl_online = ret;
|
|
|
|
/* Don't bail out if PSys is not supported */
|
|
rapl_register_psys();
|
|
|
|
ret = register_pm_notifier(&rapl_pm_notifier);
|
|
if (ret)
|
|
goto err_unreg_all;
|
|
|
|
return 0;
|
|
|
|
err_unreg_all:
|
|
cpuhp_remove_state(pcap_rapl_online);
|
|
|
|
err_unreg:
|
|
rapl_unregister_powercap();
|
|
return ret;
|
|
}
|
|
|
|
static void __exit rapl_exit(void)
|
|
{
|
|
unregister_pm_notifier(&rapl_pm_notifier);
|
|
cpuhp_remove_state(pcap_rapl_online);
|
|
rapl_unregister_powercap();
|
|
}
|
|
|
|
module_init(rapl_init);
|
|
module_exit(rapl_exit);
|
|
|
|
MODULE_DESCRIPTION("Driver for Intel RAPL (Running Average Power Limit)");
|
|
MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>");
|
|
MODULE_LICENSE("GPL v2");
|