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44c9225729
Introduce XIP (eXecute In Place) support for RISC-V platforms. It allows code to be executed directly from non-volatile storage directly addressable by the CPU, such as QSPI NOR flash which can be found on many RISC-V platforms. This makes way for significant optimization of RAM footprint. The XIP kernel is not compressed since it has to run directly from flash, so it will occupy more space on the non-volatile storage. The physical flash address used to link the kernel object files and for storing it has to be known at compile time and is represented by a Kconfig option. XIP on RISC-V will for the time being only work on MMU-enabled kernels. Signed-off-by: Vitaly Wool <vitaly.wool@konsulko.com> [Alex: Rebase on top of "Move kernel mapping outside the linear mapping" ] Signed-off-by: Alexandre Ghiti <alex@ghiti.fr> [Palmer: disable XIP for allyesconfig] Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
23 lines
490 B
C
23 lines
490 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019 SiFive, Inc.
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*/
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#ifndef __ASM_HEAD_H
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#define __ASM_HEAD_H
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#include <linux/linkage.h>
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#include <linux/init.h>
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extern atomic_t hart_lottery;
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asmlinkage void do_page_fault(struct pt_regs *regs);
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asmlinkage void __init setup_vm(uintptr_t dtb_pa);
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#ifdef CONFIG_XIP_KERNEL
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asmlinkage void __init __copy_data(void);
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#endif
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extern void *__cpu_up_stack_pointer[];
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extern void *__cpu_up_task_pointer[];
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#endif /* __ASM_HEAD_H */
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