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cebef18833
Add MT8192 camsys and camsys raw clock providers Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210726105719.15793-12-chun-jie.chen@mediatek.com Reviewed-by: Ikjoon Jang <ikjn@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
108 lines
3.2 KiB
C
108 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// Copyright (c) 2021 MediaTek Inc.
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// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
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#include <linux/clk-provider.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt8192-clk.h>
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static const struct mtk_gate_regs cam_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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#define GATE_CAM(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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static const struct mtk_gate cam_clks[] = {
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GATE_CAM(CLK_CAM_LARB13, "cam_larb13", "cam_sel", 0),
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GATE_CAM(CLK_CAM_DFP_VAD, "cam_dfp_vad", "cam_sel", 1),
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GATE_CAM(CLK_CAM_LARB14, "cam_larb14", "cam_sel", 2),
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GATE_CAM(CLK_CAM_CAM, "cam_cam", "cam_sel", 6),
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GATE_CAM(CLK_CAM_CAMTG, "cam_camtg", "cam_sel", 7),
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GATE_CAM(CLK_CAM_SENINF, "cam_seninf", "cam_sel", 8),
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GATE_CAM(CLK_CAM_CAMSV0, "cam_camsv0", "cam_sel", 9),
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GATE_CAM(CLK_CAM_CAMSV1, "cam_camsv1", "cam_sel", 10),
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GATE_CAM(CLK_CAM_CAMSV2, "cam_camsv2", "cam_sel", 11),
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GATE_CAM(CLK_CAM_CAMSV3, "cam_camsv3", "cam_sel", 12),
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GATE_CAM(CLK_CAM_CCU0, "cam_ccu0", "cam_sel", 13),
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GATE_CAM(CLK_CAM_CCU1, "cam_ccu1", "cam_sel", 14),
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GATE_CAM(CLK_CAM_MRAW0, "cam_mraw0", "cam_sel", 15),
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GATE_CAM(CLK_CAM_FAKE_ENG, "cam_fake_eng", "cam_sel", 17),
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GATE_CAM(CLK_CAM_CCU_GALS, "cam_ccu_gals", "cam_sel", 18),
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GATE_CAM(CLK_CAM_CAM2MM_GALS, "cam2mm_gals", "cam_sel", 19),
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};
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static const struct mtk_gate cam_rawa_clks[] = {
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GATE_CAM(CLK_CAM_RAWA_LARBX, "cam_rawa_larbx", "cam_sel", 0),
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GATE_CAM(CLK_CAM_RAWA_CAM, "cam_rawa_cam", "cam_sel", 1),
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GATE_CAM(CLK_CAM_RAWA_CAMTG, "cam_rawa_camtg", "cam_sel", 2),
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};
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static const struct mtk_gate cam_rawb_clks[] = {
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GATE_CAM(CLK_CAM_RAWB_LARBX, "cam_rawb_larbx", "cam_sel", 0),
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GATE_CAM(CLK_CAM_RAWB_CAM, "cam_rawb_cam", "cam_sel", 1),
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GATE_CAM(CLK_CAM_RAWB_CAMTG, "cam_rawb_camtg", "cam_sel", 2),
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};
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static const struct mtk_gate cam_rawc_clks[] = {
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GATE_CAM(CLK_CAM_RAWC_LARBX, "cam_rawc_larbx", "cam_sel", 0),
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GATE_CAM(CLK_CAM_RAWC_CAM, "cam_rawc_cam", "cam_sel", 1),
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GATE_CAM(CLK_CAM_RAWC_CAMTG, "cam_rawc_camtg", "cam_sel", 2),
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};
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static const struct mtk_clk_desc cam_desc = {
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.clks = cam_clks,
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.num_clks = ARRAY_SIZE(cam_clks),
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};
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static const struct mtk_clk_desc cam_rawa_desc = {
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.clks = cam_rawa_clks,
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.num_clks = ARRAY_SIZE(cam_rawa_clks),
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};
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static const struct mtk_clk_desc cam_rawb_desc = {
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.clks = cam_rawb_clks,
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.num_clks = ARRAY_SIZE(cam_rawb_clks),
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};
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static const struct mtk_clk_desc cam_rawc_desc = {
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.clks = cam_rawc_clks,
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.num_clks = ARRAY_SIZE(cam_rawc_clks),
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};
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static const struct of_device_id of_match_clk_mt8192_cam[] = {
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{
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.compatible = "mediatek,mt8192-camsys",
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.data = &cam_desc,
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}, {
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.compatible = "mediatek,mt8192-camsys_rawa",
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.data = &cam_rawa_desc,
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}, {
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.compatible = "mediatek,mt8192-camsys_rawb",
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.data = &cam_rawb_desc,
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}, {
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.compatible = "mediatek,mt8192-camsys_rawc",
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.data = &cam_rawc_desc,
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}, {
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/* sentinel */
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}
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};
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static struct platform_driver clk_mt8192_cam_drv = {
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.probe = mtk_clk_simple_probe,
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.driver = {
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.name = "clk-mt8192-cam",
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.of_match_table = of_match_clk_mt8192_cam,
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},
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};
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builtin_platform_driver(clk_mt8192_cam_drv);
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