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In preparation for making the clockevents core NTP correction aware, all clockevent device drivers must set ->min_delta_ticks and ->max_delta_ticks rather than ->min_delta_ns and ->max_delta_ns: a clockevent device's rate is going to change dynamically and thus, the ratio of ns to ticks ceases to stay invariant. Make the numachip clockevent driver initialize these fields properly. This patch alone doesn't introduce any change in functionality as the clockevents core still looks exclusively at the (untouched) ->min_delta_ns and ->max_delta_ns. As soon as this has changed, a followup patch will purge the initialization of ->min_delta_ns and ->max_delta_ns from this driver. Cc: Ingo Molnar <mingo@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Richard Cochran <richardcochran@gmail.com> Cc: Prarit Bhargava <prarit@redhat.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Nicolai Stange <nicstange@gmail.com> Signed-off-by: John Stultz <john.stultz@linaro.org>
98 lines
2.7 KiB
C
98 lines
2.7 KiB
C
/*
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*
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* Copyright (C) 2015 Numascale AS. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/clockchips.h>
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#include <asm/irq.h>
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#include <asm/numachip/numachip.h>
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#include <asm/numachip/numachip_csr.h>
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static DEFINE_PER_CPU(struct clock_event_device, numachip2_ced);
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static cycles_t numachip2_timer_read(struct clocksource *cs)
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{
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return numachip2_read64_lcsr(NUMACHIP2_TIMER_NOW);
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}
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static struct clocksource numachip2_clocksource = {
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.name = "numachip2",
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.rating = 295,
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.read = numachip2_timer_read,
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.mask = CLOCKSOURCE_MASK(64),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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.mult = 1,
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.shift = 0,
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};
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static int numachip2_set_next_event(unsigned long delta, struct clock_event_device *ced)
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{
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numachip2_write64_lcsr(NUMACHIP2_TIMER_DEADLINE + numachip2_timer(),
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delta);
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return 0;
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}
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static struct clock_event_device numachip2_clockevent = {
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.name = "numachip2",
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.rating = 400,
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.set_next_event = numachip2_set_next_event,
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.mult = 1,
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.shift = 0,
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.min_delta_ns = 1250,
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.min_delta_ticks = 1250,
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.max_delta_ns = LONG_MAX,
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.max_delta_ticks = LONG_MAX,
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};
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static void numachip_timer_interrupt(void)
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{
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struct clock_event_device *ced = this_cpu_ptr(&numachip2_ced);
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ced->event_handler(ced);
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}
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static __init void numachip_timer_each(struct work_struct *work)
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{
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unsigned local_apicid = __this_cpu_read(x86_cpu_to_apicid) & 0xff;
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struct clock_event_device *ced = this_cpu_ptr(&numachip2_ced);
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/* Setup IPI vector to local core and relative timing mode */
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numachip2_write64_lcsr(NUMACHIP2_TIMER_INT + numachip2_timer(),
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(3 << 22) | (X86_PLATFORM_IPI_VECTOR << 14) |
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(local_apicid << 6));
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*ced = numachip2_clockevent;
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ced->cpumask = cpumask_of(smp_processor_id());
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clockevents_register_device(ced);
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}
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static int __init numachip_timer_init(void)
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{
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if (numachip_system != 2)
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return -ENODEV;
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/* Reset timer */
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numachip2_write64_lcsr(NUMACHIP2_TIMER_RESET, 0);
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clocksource_register_hz(&numachip2_clocksource, NSEC_PER_SEC);
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/* Setup per-cpu clockevents */
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x86_platform_ipi_callback = numachip_timer_interrupt;
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schedule_on_each_cpu(&numachip_timer_each);
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return 0;
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}
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arch_initcall(numachip_timer_init);
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