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c347d12cd1
In the SH-3/4 TLB access violation path we were enabling IRQs before
the call in to trace_hardirqs_on(), which ended up triggering:
if (DEBUG_LOCKS_WARN_ON(!irqs_disabled()))
return;
in kernel/lockdep.c:2031. Fix this up by removing the early re-enable,
we were already re-enabling IRQs post-trace_hardirqs_on() already, so
the semantics are now as was initially intended.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
553 lines
11 KiB
ArmAsm
553 lines
11 KiB
ArmAsm
/*
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* arch/sh/kernel/cpu/sh3/entry.S
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*
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* Copyright (C) 1999, 2000, 2002 Niibe Yutaka
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* Copyright (C) 2003 - 2006 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/sys.h>
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#include <linux/errno.h>
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#include <linux/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/thread_info.h>
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#include <asm/cpu/mmu_context.h>
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#include <asm/unistd.h>
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! NOTE:
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! GNU as (as of 2.9.1) changes bf/s into bt/s and bra, when the address
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! to be jumped is too far, but it causes illegal slot exception.
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/*
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* entry.S contains the system-call and fault low-level handling routines.
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* This also contains the timer-interrupt handler, as well as all interrupts
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* and faults that can result in a task-switch.
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*
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* NOTE: This code handles signal-recognition, which happens every time
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* after a timer-interrupt and after each system call.
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*
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* NOTE: This code uses a convention that instructions in the delay slot
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* of a transfer-control instruction are indented by an extra space, thus:
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*
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* jmp @k0 ! control-transfer instruction
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* ldc k1, ssr ! delay slot
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*
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* Stack layout in 'ret_from_syscall':
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* ptrace needs to have all regs on the stack.
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* if the order here is changed, it needs to be
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* updated in ptrace.c and ptrace.h
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*
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* r0
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* ...
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* r15 = stack pointer
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* spc
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* pr
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* ssr
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* gbr
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* mach
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* macl
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* syscall #
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*
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*/
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#if defined(CONFIG_KGDB_NMI)
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NMI_VEC = 0x1c0 ! Must catch early for debounce
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#endif
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/* Offsets to the stack */
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OFF_R0 = 0 /* Return value. New ABI also arg4 */
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OFF_R1 = 4 /* New ABI: arg5 */
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OFF_R2 = 8 /* New ABI: arg6 */
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OFF_R3 = 12 /* New ABI: syscall_nr */
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OFF_R4 = 16 /* New ABI: arg0 */
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OFF_R5 = 20 /* New ABI: arg1 */
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OFF_R6 = 24 /* New ABI: arg2 */
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OFF_R7 = 28 /* New ABI: arg3 */
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OFF_SP = (15*4)
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OFF_PC = (16*4)
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OFF_SR = (16*4+8)
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OFF_TRA = (16*4+6*4)
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#define k0 r0
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#define k1 r1
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#define k2 r2
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#define k3 r3
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#define k4 r4
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#define g_imask r6 /* r6_bank1 */
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#define k_g_imask r6_bank /* r6_bank1 */
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#define current r7 /* r7_bank1 */
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#include <asm/entry-macros.S>
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/*
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* Kernel mode register usage:
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* k0 scratch
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* k1 scratch
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* k2 scratch (Exception code)
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* k3 scratch (Return address)
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* k4 scratch
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* k5 reserved
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* k6 Global Interrupt Mask (0--15 << 4)
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* k7 CURRENT_THREAD_INFO (pointer to current thread info)
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*/
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!
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! TLB Miss / Initial Page write exception handling
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! _and_
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! TLB hits, but the access violate the protection.
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! It can be valid access, such as stack grow and/or C-O-W.
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!
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!
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! Find the pmd/pte entry and loadtlb
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! If it's not found, cause address error (SEGV)
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!
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! Although this could be written in assembly language (and it'd be faster),
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! this first version depends *much* on C implementation.
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!
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#if defined(CONFIG_MMU)
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.align 2
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ENTRY(tlb_miss_load)
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bra call_dpf
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mov #0, r5
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.align 2
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ENTRY(tlb_miss_store)
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bra call_dpf
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mov #1, r5
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.align 2
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ENTRY(initial_page_write)
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bra call_dpf
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mov #1, r5
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.align 2
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ENTRY(tlb_protection_violation_load)
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bra call_dpf
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mov #0, r5
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.align 2
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ENTRY(tlb_protection_violation_store)
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bra call_dpf
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mov #1, r5
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call_dpf:
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mov.l 1f, r0
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mov r5, r8
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mov.l @r0, r6
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mov r6, r9
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mov.l 2f, r0
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sts pr, r10
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jsr @r0
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mov r15, r4
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!
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tst r0, r0
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bf/s 0f
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lds r10, pr
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rts
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nop
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0: mov.l 3f, r0
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mov r9, r6
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mov r8, r5
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jmp @r0
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mov r15, r4
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.align 2
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1: .long MMU_TEA
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2: .long __do_page_fault
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3: .long do_page_fault
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.align 2
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ENTRY(address_error_load)
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bra call_dae
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mov #0,r5 ! writeaccess = 0
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.align 2
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ENTRY(address_error_store)
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bra call_dae
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mov #1,r5 ! writeaccess = 1
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.align 2
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call_dae:
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mov.l 1f, r0
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mov.l @r0, r6 ! address
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mov.l 2f, r0
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jmp @r0
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mov r15, r4 ! regs
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.align 2
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1: .long MMU_TEA
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2: .long do_address_error
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#endif /* CONFIG_MMU */
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#if defined(CONFIG_SH_STANDARD_BIOS)
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/* Unwind the stack and jmp to the debug entry */
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ENTRY(sh_bios_handler)
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mov.l @r15+, r0
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mov.l @r15+, r1
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mov.l @r15+, r2
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mov.l @r15+, r3
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mov.l @r15+, r4
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mov.l @r15+, r5
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mov.l @r15+, r6
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mov.l @r15+, r7
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stc sr, r8
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mov.l 1f, r9 ! BL =1, RB=1, IMASK=0x0F
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or r9, r8
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ldc r8, sr ! here, change the register bank
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mov.l @r15+, r8
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mov.l @r15+, r9
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mov.l @r15+, r10
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mov.l @r15+, r11
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mov.l @r15+, r12
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mov.l @r15+, r13
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mov.l @r15+, r14
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mov.l @r15+, k0
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ldc.l @r15+, spc
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lds.l @r15+, pr
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mov.l @r15+, k1
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ldc.l @r15+, gbr
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lds.l @r15+, mach
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lds.l @r15+, macl
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mov k0, r15
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!
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mov.l 2f, k0
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mov.l @k0, k0
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jmp @k0
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ldc k1, ssr
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.align 2
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1: .long 0x300000f0
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2: .long gdb_vbr_vector
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#endif /* CONFIG_SH_STANDARD_BIOS */
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restore_all:
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mov.l @r15+, r0
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mov.l @r15+, r1
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mov.l @r15+, r2
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mov.l @r15+, r3
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mov.l @r15+, r4
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mov.l @r15+, r5
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mov.l @r15+, r6
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mov.l @r15+, r7
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!
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stc sr, r8
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mov.l 7f, r9
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or r9, r8 ! BL =1, RB=1
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ldc r8, sr ! here, change the register bank
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!
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mov.l @r15+, r8
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mov.l @r15+, r9
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mov.l @r15+, r10
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mov.l @r15+, r11
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mov.l @r15+, r12
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mov.l @r15+, r13
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mov.l @r15+, r14
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mov.l @r15+, k4 ! original stack pointer
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ldc.l @r15+, spc
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lds.l @r15+, pr
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mov.l @r15+, k3 ! original SR
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ldc.l @r15+, gbr
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lds.l @r15+, mach
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lds.l @r15+, macl
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add #4, r15 ! Skip syscall number
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!
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#ifdef CONFIG_SH_DSP
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mov.l @r15+, k0 ! DSP mode marker
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mov.l 5f, k1
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cmp/eq k0, k1 ! Do we have a DSP stack frame?
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bf skip_restore
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stc sr, k0 ! Enable CPU DSP mode
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or k1, k0 ! (within kernel it may be disabled)
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ldc k0, sr
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mov r2, k0 ! Backup r2
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! Restore DSP registers from stack
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mov r15, r2
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movs.l @r2+, a1
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movs.l @r2+, a0g
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movs.l @r2+, a1g
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movs.l @r2+, m0
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movs.l @r2+, m1
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mov r2, r15
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lds.l @r15+, a0
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lds.l @r15+, x0
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lds.l @r15+, x1
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lds.l @r15+, y0
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lds.l @r15+, y1
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lds.l @r15+, dsr
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ldc.l @r15+, rs
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ldc.l @r15+, re
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ldc.l @r15+, mod
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mov k0, r2 ! Restore r2
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skip_restore:
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#endif
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!
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! Calculate new SR value
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mov k3, k2 ! original SR value
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mov #0xf0, k1
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extu.b k1, k1
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not k1, k1
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and k1, k2 ! Mask orignal SR value
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!
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mov k3, k0 ! Calculate IMASK-bits
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shlr2 k0
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and #0x3c, k0
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cmp/eq #0x3c, k0
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bt/s 6f
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shll2 k0
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mov g_imask, k0
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!
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6: or k0, k2 ! Set the IMASK-bits
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ldc k2, ssr
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!
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#if defined(CONFIG_KGDB_NMI)
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! Clear in_nmi
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mov.l 6f, k0
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mov #0, k1
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mov.b k1, @k0
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#endif
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mov.l @r15+, k2 ! restore EXPEVT
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mov k4, r15
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rte
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nop
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.align 2
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5: .long 0x00001000 ! DSP
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#ifdef CONFIG_KGDB_NMI
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6: .long in_nmi
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#endif
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7: .long 0x30000000
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! common exception handler
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#include "../../entry-common.S"
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! Exception Vector Base
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!
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! Should be aligned page boundary.
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!
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.balign 4096,0,4096
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ENTRY(vbr_base)
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.long 0
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!
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.balign 256,0,256
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general_exception:
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mov.l 1f, k2
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mov.l 2f, k3
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#ifdef CONFIG_CPU_SUBTYPE_SHX3
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mov.l @k2, k2
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! Is EXPEVT larger than 0x800?
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mov #0x8, k0
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shll8 k0
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cmp/hs k0, k2
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bf 0f
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! then add 0x580 (k2 is 0xd80 or 0xda0)
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mov #0x58, k0
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shll2 k0
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shll2 k0
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add k0, k2
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0:
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bra handle_exception
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nop
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#else
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bra handle_exception
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mov.l @k2, k2
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#endif
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.align 2
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1: .long EXPEVT
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2: .long ret_from_exception
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!
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!
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.balign 1024,0,1024
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tlb_miss:
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mov.l 1f, k2
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mov.l 4f, k3
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bra handle_exception
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mov.l @k2, k2
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!
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.balign 512,0,512
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interrupt:
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mov.l 2f, k2
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mov.l 3f, k3
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#if defined(CONFIG_KGDB_NMI)
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! Debounce (filter nested NMI)
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mov.l @k2, k0
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mov.l 5f, k1
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cmp/eq k1, k0
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bf 0f
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mov.l 6f, k1
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tas.b @k1
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bt 0f
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rte
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nop
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.align 2
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5: .long NMI_VEC
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6: .long in_nmi
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0:
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#endif /* defined(CONFIG_KGDB_NMI) */
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bra handle_exception
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mov #-1, k2 ! interrupt exception marker
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.align 2
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1: .long EXPEVT
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2: .long INTEVT
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3: .long ret_from_irq
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4: .long ret_from_exception
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!
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!
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.align 2
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ENTRY(handle_exception)
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! Using k0, k1 for scratch registers (r0_bank1, r1_bank),
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! save all registers onto stack.
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!
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stc ssr, k0 ! Is it from kernel space?
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shll k0 ! Check MD bit (bit30) by shifting it into...
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shll k0 ! ...the T bit
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bt/s 1f ! It's a kernel to kernel transition.
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mov r15, k0 ! save original stack to k0
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/* User space to kernel */
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mov #(THREAD_SIZE >> 10), k1
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shll8 k1 ! k1 := THREAD_SIZE
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shll2 k1
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add current, k1
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mov k1, r15 ! change to kernel stack
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!
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1: mov.l 2f, k1
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!
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#ifdef CONFIG_SH_DSP
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mov.l r2, @-r15 ! Save r2, we need another reg
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stc sr, k4
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mov.l 1f, r2
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tst r2, k4 ! Check if in DSP mode
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mov.l @r15+, r2 ! Restore r2 now
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bt/s skip_save
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mov #0, k4 ! Set marker for no stack frame
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mov r2, k4 ! Backup r2 (in k4) for later
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! Save DSP registers on stack
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stc.l mod, @-r15
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stc.l re, @-r15
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stc.l rs, @-r15
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sts.l dsr, @-r15
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sts.l y1, @-r15
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sts.l y0, @-r15
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sts.l x1, @-r15
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sts.l x0, @-r15
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sts.l a0, @-r15
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! GAS is broken, does not generate correct "movs.l Ds,@-As" instr.
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! FIXME: Make sure that this is still the case with newer toolchains,
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! as we're not at all interested in supporting ancient toolchains at
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! this point. -- PFM.
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mov r15, r2
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.word 0xf653 ! movs.l a1, @-r2
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.word 0xf6f3 ! movs.l a0g, @-r2
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.word 0xf6d3 ! movs.l a1g, @-r2
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.word 0xf6c3 ! movs.l m0, @-r2
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.word 0xf6e3 ! movs.l m1, @-r2
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mov r2, r15
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mov k4, r2 ! Restore r2
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mov.l 1f, k4 ! Force DSP stack frame
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skip_save:
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mov.l k4, @-r15 ! Push DSP mode marker onto stack
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#endif
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! Save the user registers on the stack.
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mov.l k2, @-r15 ! EXPEVT
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mov #-1, k4
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mov.l k4, @-r15 ! set TRA (default: -1)
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!
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sts.l macl, @-r15
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sts.l mach, @-r15
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stc.l gbr, @-r15
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stc.l ssr, @-r15
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sts.l pr, @-r15
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stc.l spc, @-r15
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!
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lds k3, pr ! Set the return address to pr
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!
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mov.l k0, @-r15 ! save orignal stack
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mov.l r14, @-r15
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mov.l r13, @-r15
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mov.l r12, @-r15
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mov.l r11, @-r15
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mov.l r10, @-r15
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mov.l r9, @-r15
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mov.l r8, @-r15
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!
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stc sr, r8 ! Back to normal register bank, and
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or k1, r8 ! Block all interrupts
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mov.l 3f, k1
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and k1, r8 ! ...
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ldc r8, sr ! ...changed here.
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!
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mov.l r7, @-r15
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mov.l r6, @-r15
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mov.l r5, @-r15
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mov.l r4, @-r15
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mov.l r3, @-r15
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mov.l r2, @-r15
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mov.l r1, @-r15
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mov.l r0, @-r15
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/*
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* This gets a bit tricky.. in the INTEVT case we don't want to use
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* the VBR offset as a destination in the jump call table, since all
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* of the destinations are the same. In this case, (interrupt) sets
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* a marker in r2 (now r2_bank since SR.RB changed), which we check
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* to determine the exception type. For all other exceptions, we
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* forcibly read EXPEVT from memory and fix up the jump address, in
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* the interrupt exception case we jump to do_IRQ() and defer the
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* INTEVT read until there. As a bonus, we can also clean up the SR.RB
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* checks that do_IRQ() was doing..
|
|
*/
|
|
stc r2_bank, r8
|
|
cmp/pz r8
|
|
bf interrupt_exception
|
|
shlr2 r8
|
|
shlr r8
|
|
mov.l 4f, r9
|
|
add r8, r9
|
|
mov.l @r9, r9
|
|
jmp @r9
|
|
nop
|
|
rts
|
|
nop
|
|
|
|
.align 2
|
|
1: .long 0x00001000 ! DSP=1
|
|
2: .long 0x000080f0 ! FD=1, IMASK=15
|
|
3: .long 0xcfffffff ! RB=0, BL=0
|
|
4: .long exception_handling_table
|
|
|
|
interrupt_exception:
|
|
mov.l 1f, r9
|
|
mov.l 2f, r4
|
|
mov.l @r4, r4
|
|
jmp @r9
|
|
mov r15, r5
|
|
rts
|
|
nop
|
|
|
|
.align 2
|
|
1: .long do_IRQ
|
|
2: .long INTEVT
|
|
|
|
.align 2
|
|
ENTRY(exception_none)
|
|
rts
|
|
nop
|