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f5f7eac41d
Pass the original flags to rwlock arch-code, so that it can re-enable interrupts if implemented for that architecture. Initially, make __raw_read_lock_flags and __raw_write_lock_flags stubs which just do the same thing as non-flags variants. Signed-off-by: Petr Tesarik <ptesarik@suse.cz> Signed-off-by: Robin Holt <holt@sgi.com> Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: <linux-arch@vger.kernel.org> Acked-by: Ingo Molnar <mingo@elte.hu> Cc: "Luck, Tony" <tony.luck@intel.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
491 lines
12 KiB
C
491 lines
12 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1999, 2000, 06 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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*/
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#ifndef _ASM_SPINLOCK_H
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#define _ASM_SPINLOCK_H
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#include <linux/compiler.h>
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#include <asm/barrier.h>
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#include <asm/war.h>
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/*
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* Your basic SMP spinlocks, allowing only a single CPU anywhere
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*
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* Simple spin lock operations. There are two variants, one clears IRQ's
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* on the local processor, one does not.
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*
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* These are fair FIFO ticket locks
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*
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* (the type definitions are in asm/spinlock_types.h)
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*/
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/*
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* Ticket locks are conceptually two parts, one indicating the current head of
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* the queue, and the other indicating the current tail. The lock is acquired
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* by atomically noting the tail and incrementing it by one (thus adding
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* ourself to the queue and noting our position), then waiting until the head
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* becomes equal to the the initial value of the tail.
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*/
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static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
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{
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unsigned int counters = ACCESS_ONCE(lock->lock);
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return ((counters >> 14) ^ counters) & 0x1fff;
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}
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#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
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#define __raw_spin_unlock_wait(x) \
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while (__raw_spin_is_locked(x)) { cpu_relax(); }
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static inline int __raw_spin_is_contended(raw_spinlock_t *lock)
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{
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unsigned int counters = ACCESS_ONCE(lock->lock);
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return (((counters >> 14) - counters) & 0x1fff) > 1;
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}
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#define __raw_spin_is_contended __raw_spin_is_contended
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static inline void __raw_spin_lock(raw_spinlock_t *lock)
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{
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int my_ticket;
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int tmp;
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if (R10000_LLSC_WAR) {
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__asm__ __volatile__ (
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" .set push # __raw_spin_lock \n"
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" .set noreorder \n"
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" \n"
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"1: ll %[ticket], %[ticket_ptr] \n"
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" addiu %[my_ticket], %[ticket], 0x4000 \n"
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" sc %[my_ticket], %[ticket_ptr] \n"
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" beqzl %[my_ticket], 1b \n"
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" nop \n"
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" srl %[my_ticket], %[ticket], 14 \n"
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" andi %[my_ticket], %[my_ticket], 0x1fff \n"
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" andi %[ticket], %[ticket], 0x1fff \n"
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" bne %[ticket], %[my_ticket], 4f \n"
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" subu %[ticket], %[my_ticket], %[ticket] \n"
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"2: \n"
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" .subsection 2 \n"
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"4: andi %[ticket], %[ticket], 0x1fff \n"
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" sll %[ticket], 5 \n"
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" \n"
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"6: bnez %[ticket], 6b \n"
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" subu %[ticket], 1 \n"
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" \n"
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" lw %[ticket], %[ticket_ptr] \n"
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" andi %[ticket], %[ticket], 0x1fff \n"
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" beq %[ticket], %[my_ticket], 2b \n"
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" subu %[ticket], %[my_ticket], %[ticket] \n"
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" b 4b \n"
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" subu %[ticket], %[ticket], 1 \n"
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" .previous \n"
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" .set pop \n"
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: [ticket_ptr] "+m" (lock->lock),
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[ticket] "=&r" (tmp),
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[my_ticket] "=&r" (my_ticket));
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} else {
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__asm__ __volatile__ (
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" .set push # __raw_spin_lock \n"
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" .set noreorder \n"
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" \n"
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" ll %[ticket], %[ticket_ptr] \n"
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"1: addiu %[my_ticket], %[ticket], 0x4000 \n"
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" sc %[my_ticket], %[ticket_ptr] \n"
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" beqz %[my_ticket], 3f \n"
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" nop \n"
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" srl %[my_ticket], %[ticket], 14 \n"
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" andi %[my_ticket], %[my_ticket], 0x1fff \n"
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" andi %[ticket], %[ticket], 0x1fff \n"
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" bne %[ticket], %[my_ticket], 4f \n"
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" subu %[ticket], %[my_ticket], %[ticket] \n"
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"2: \n"
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" .subsection 2 \n"
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"3: b 1b \n"
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" ll %[ticket], %[ticket_ptr] \n"
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" \n"
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"4: andi %[ticket], %[ticket], 0x1fff \n"
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" sll %[ticket], 5 \n"
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" \n"
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"6: bnez %[ticket], 6b \n"
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" subu %[ticket], 1 \n"
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" \n"
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" lw %[ticket], %[ticket_ptr] \n"
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" andi %[ticket], %[ticket], 0x1fff \n"
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" beq %[ticket], %[my_ticket], 2b \n"
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" subu %[ticket], %[my_ticket], %[ticket] \n"
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" b 4b \n"
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" subu %[ticket], %[ticket], 1 \n"
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" .previous \n"
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" .set pop \n"
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: [ticket_ptr] "+m" (lock->lock),
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[ticket] "=&r" (tmp),
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[my_ticket] "=&r" (my_ticket));
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}
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smp_llsc_mb();
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}
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static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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{
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int tmp;
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smp_llsc_mb();
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if (R10000_LLSC_WAR) {
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__asm__ __volatile__ (
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" # __raw_spin_unlock \n"
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"1: ll %[ticket], %[ticket_ptr] \n"
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" addiu %[ticket], %[ticket], 1 \n"
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" ori %[ticket], %[ticket], 0x2000 \n"
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" xori %[ticket], %[ticket], 0x2000 \n"
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" sc %[ticket], %[ticket_ptr] \n"
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" beqzl %[ticket], 1b \n"
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: [ticket_ptr] "+m" (lock->lock),
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[ticket] "=&r" (tmp));
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} else {
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__asm__ __volatile__ (
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" .set push # __raw_spin_unlock \n"
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" .set noreorder \n"
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" \n"
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" ll %[ticket], %[ticket_ptr] \n"
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"1: addiu %[ticket], %[ticket], 1 \n"
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" ori %[ticket], %[ticket], 0x2000 \n"
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" xori %[ticket], %[ticket], 0x2000 \n"
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" sc %[ticket], %[ticket_ptr] \n"
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" beqz %[ticket], 2f \n"
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" nop \n"
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" \n"
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" .subsection 2 \n"
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"2: b 1b \n"
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" ll %[ticket], %[ticket_ptr] \n"
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" .previous \n"
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" .set pop \n"
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: [ticket_ptr] "+m" (lock->lock),
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[ticket] "=&r" (tmp));
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}
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}
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static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock)
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{
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int tmp, tmp2, tmp3;
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if (R10000_LLSC_WAR) {
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__asm__ __volatile__ (
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" .set push # __raw_spin_trylock \n"
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" .set noreorder \n"
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" \n"
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"1: ll %[ticket], %[ticket_ptr] \n"
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" srl %[my_ticket], %[ticket], 14 \n"
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" andi %[my_ticket], %[my_ticket], 0x1fff \n"
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" andi %[now_serving], %[ticket], 0x1fff \n"
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" bne %[my_ticket], %[now_serving], 3f \n"
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" addiu %[ticket], %[ticket], 0x4000 \n"
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" sc %[ticket], %[ticket_ptr] \n"
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" beqzl %[ticket], 1b \n"
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" li %[ticket], 1 \n"
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"2: \n"
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" .subsection 2 \n"
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"3: b 2b \n"
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" li %[ticket], 0 \n"
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" .previous \n"
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" .set pop \n"
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: [ticket_ptr] "+m" (lock->lock),
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[ticket] "=&r" (tmp),
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[my_ticket] "=&r" (tmp2),
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[now_serving] "=&r" (tmp3));
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} else {
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__asm__ __volatile__ (
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" .set push # __raw_spin_trylock \n"
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" .set noreorder \n"
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" \n"
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" ll %[ticket], %[ticket_ptr] \n"
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"1: srl %[my_ticket], %[ticket], 14 \n"
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" andi %[my_ticket], %[my_ticket], 0x1fff \n"
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" andi %[now_serving], %[ticket], 0x1fff \n"
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" bne %[my_ticket], %[now_serving], 3f \n"
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" addiu %[ticket], %[ticket], 0x4000 \n"
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" sc %[ticket], %[ticket_ptr] \n"
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" beqz %[ticket], 4f \n"
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" li %[ticket], 1 \n"
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"2: \n"
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" .subsection 2 \n"
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"3: b 2b \n"
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" li %[ticket], 0 \n"
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"4: b 1b \n"
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" ll %[ticket], %[ticket_ptr] \n"
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" .previous \n"
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" .set pop \n"
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: [ticket_ptr] "+m" (lock->lock),
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[ticket] "=&r" (tmp),
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[my_ticket] "=&r" (tmp2),
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[now_serving] "=&r" (tmp3));
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}
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smp_llsc_mb();
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return tmp;
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}
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/*
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* Read-write spinlocks, allowing multiple readers but only one writer.
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*
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* NOTE! it is quite common to have readers in interrupts but no interrupt
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* writers. For those circumstances we can "mix" irq-safe locks - any writer
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* needs to get a irq-safe write-lock, but readers can get non-irqsafe
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* read-locks.
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*/
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/*
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* read_can_lock - would read_trylock() succeed?
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* @lock: the rwlock in question.
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*/
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#define __raw_read_can_lock(rw) ((rw)->lock >= 0)
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/*
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* write_can_lock - would write_trylock() succeed?
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* @lock: the rwlock in question.
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*/
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#define __raw_write_can_lock(rw) (!(rw)->lock)
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static inline void __raw_read_lock(raw_rwlock_t *rw)
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{
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unsigned int tmp;
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if (R10000_LLSC_WAR) {
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__asm__ __volatile__(
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" .set noreorder # __raw_read_lock \n"
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"1: ll %1, %2 \n"
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" bltz %1, 1b \n"
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" addu %1, 1 \n"
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" sc %1, %0 \n"
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" beqzl %1, 1b \n"
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" nop \n"
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" .set reorder \n"
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: "=m" (rw->lock), "=&r" (tmp)
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: "m" (rw->lock)
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: "memory");
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} else {
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__asm__ __volatile__(
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" .set noreorder # __raw_read_lock \n"
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"1: ll %1, %2 \n"
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" bltz %1, 2f \n"
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" addu %1, 1 \n"
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" sc %1, %0 \n"
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" beqz %1, 1b \n"
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" nop \n"
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" .subsection 2 \n"
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"2: ll %1, %2 \n"
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" bltz %1, 2b \n"
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" addu %1, 1 \n"
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" b 1b \n"
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" nop \n"
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" .previous \n"
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" .set reorder \n"
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: "=m" (rw->lock), "=&r" (tmp)
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: "m" (rw->lock)
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: "memory");
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}
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smp_llsc_mb();
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}
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/* Note the use of sub, not subu which will make the kernel die with an
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overflow exception if we ever try to unlock an rwlock that is already
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unlocked or is being held by a writer. */
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static inline void __raw_read_unlock(raw_rwlock_t *rw)
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{
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unsigned int tmp;
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smp_llsc_mb();
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if (R10000_LLSC_WAR) {
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__asm__ __volatile__(
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"1: ll %1, %2 # __raw_read_unlock \n"
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" sub %1, 1 \n"
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" sc %1, %0 \n"
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" beqzl %1, 1b \n"
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: "=m" (rw->lock), "=&r" (tmp)
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: "m" (rw->lock)
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: "memory");
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} else {
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__asm__ __volatile__(
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" .set noreorder # __raw_read_unlock \n"
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"1: ll %1, %2 \n"
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" sub %1, 1 \n"
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" sc %1, %0 \n"
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" beqz %1, 2f \n"
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" nop \n"
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" .subsection 2 \n"
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"2: b 1b \n"
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" nop \n"
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" .previous \n"
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" .set reorder \n"
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: "=m" (rw->lock), "=&r" (tmp)
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: "m" (rw->lock)
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: "memory");
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}
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}
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static inline void __raw_write_lock(raw_rwlock_t *rw)
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{
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unsigned int tmp;
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if (R10000_LLSC_WAR) {
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__asm__ __volatile__(
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" .set noreorder # __raw_write_lock \n"
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"1: ll %1, %2 \n"
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" bnez %1, 1b \n"
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" lui %1, 0x8000 \n"
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" sc %1, %0 \n"
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" beqzl %1, 1b \n"
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" nop \n"
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" .set reorder \n"
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: "=m" (rw->lock), "=&r" (tmp)
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: "m" (rw->lock)
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: "memory");
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} else {
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__asm__ __volatile__(
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" .set noreorder # __raw_write_lock \n"
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"1: ll %1, %2 \n"
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" bnez %1, 2f \n"
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" lui %1, 0x8000 \n"
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" sc %1, %0 \n"
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" beqz %1, 2f \n"
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" nop \n"
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" .subsection 2 \n"
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"2: ll %1, %2 \n"
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" bnez %1, 2b \n"
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" lui %1, 0x8000 \n"
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" b 1b \n"
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" nop \n"
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" .previous \n"
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" .set reorder \n"
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: "=m" (rw->lock), "=&r" (tmp)
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: "m" (rw->lock)
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: "memory");
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}
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smp_llsc_mb();
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}
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static inline void __raw_write_unlock(raw_rwlock_t *rw)
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{
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smp_mb();
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__asm__ __volatile__(
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" # __raw_write_unlock \n"
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" sw $0, %0 \n"
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: "=m" (rw->lock)
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: "m" (rw->lock)
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: "memory");
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}
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static inline int __raw_read_trylock(raw_rwlock_t *rw)
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{
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unsigned int tmp;
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int ret;
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if (R10000_LLSC_WAR) {
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__asm__ __volatile__(
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" .set noreorder # __raw_read_trylock \n"
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" li %2, 0 \n"
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"1: ll %1, %3 \n"
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" bltz %1, 2f \n"
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" addu %1, 1 \n"
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" sc %1, %0 \n"
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" .set reorder \n"
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" beqzl %1, 1b \n"
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" nop \n"
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__WEAK_LLSC_MB
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" li %2, 1 \n"
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"2: \n"
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: "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
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: "m" (rw->lock)
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: "memory");
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} else {
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__asm__ __volatile__(
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" .set noreorder # __raw_read_trylock \n"
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" li %2, 0 \n"
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"1: ll %1, %3 \n"
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" bltz %1, 2f \n"
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" addu %1, 1 \n"
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" sc %1, %0 \n"
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" beqz %1, 1b \n"
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" nop \n"
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" .set reorder \n"
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__WEAK_LLSC_MB
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" li %2, 1 \n"
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"2: \n"
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: "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
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: "m" (rw->lock)
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: "memory");
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}
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return ret;
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}
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static inline int __raw_write_trylock(raw_rwlock_t *rw)
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{
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unsigned int tmp;
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int ret;
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if (R10000_LLSC_WAR) {
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__asm__ __volatile__(
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" .set noreorder # __raw_write_trylock \n"
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" li %2, 0 \n"
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"1: ll %1, %3 \n"
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" bnez %1, 2f \n"
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" lui %1, 0x8000 \n"
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" sc %1, %0 \n"
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" beqzl %1, 1b \n"
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" nop \n"
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__WEAK_LLSC_MB
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" li %2, 1 \n"
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" .set reorder \n"
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"2: \n"
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: "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
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: "m" (rw->lock)
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: "memory");
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} else {
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__asm__ __volatile__(
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" .set noreorder # __raw_write_trylock \n"
|
|
" li %2, 0 \n"
|
|
"1: ll %1, %3 \n"
|
|
" bnez %1, 2f \n"
|
|
" lui %1, 0x8000 \n"
|
|
" sc %1, %0 \n"
|
|
" beqz %1, 3f \n"
|
|
" li %2, 1 \n"
|
|
"2: \n"
|
|
__WEAK_LLSC_MB
|
|
" .subsection 2 \n"
|
|
"3: b 1b \n"
|
|
" li %2, 0 \n"
|
|
" .previous \n"
|
|
" .set reorder \n"
|
|
: "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
|
|
: "m" (rw->lock)
|
|
: "memory");
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
#define __raw_read_lock_flags(lock, flags) __raw_read_lock(lock)
|
|
#define __raw_write_lock_flags(lock, flags) __raw_write_lock(lock)
|
|
|
|
#define _raw_spin_relax(lock) cpu_relax()
|
|
#define _raw_read_relax(lock) cpu_relax()
|
|
#define _raw_write_relax(lock) cpu_relax()
|
|
|
|
#endif /* _ASM_SPINLOCK_H */
|