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1727339590
The CLOCKSOURCE_OF_DECLARE macro is used widely for the timers to declare the clocksource at early stage. However, this macro is also used to initialize the clockevent if any, or the clockevent only. It was originally suggested to declare another macro to initialize a clockevent, so in order to separate the two entities even they belong to the same IP. This was not accepted because of the impact on the DT where splitting a clocksource/clockevent definition does not make sense as it is a Linux concept not a hardware description. On the other side, the clocksource has not interrupt declared while the clockevent has, so it is easy from the driver to know if the description is for a clockevent or a clocksource, IOW it could be implemented at the driver level. So instead of dealing with a named clocksource macro, let's use a more generic one: TIMER_OF_DECLARE. The patch has not functional changes. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
344 lines
8.7 KiB
C
344 lines
8.7 KiB
C
/*
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* drivers/clocksource/arm_global_timer.c
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*
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* Copyright (C) 2013 STMicroelectronics (R&D) Limited.
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* Author: Stuart Menefy <stuart.menefy@st.com>
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* Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/cpu.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/sched_clock.h>
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#include <asm/cputype.h>
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#define GT_COUNTER0 0x00
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#define GT_COUNTER1 0x04
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#define GT_CONTROL 0x08
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#define GT_CONTROL_TIMER_ENABLE BIT(0) /* this bit is NOT banked */
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#define GT_CONTROL_COMP_ENABLE BIT(1) /* banked */
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#define GT_CONTROL_IRQ_ENABLE BIT(2) /* banked */
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#define GT_CONTROL_AUTO_INC BIT(3) /* banked */
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#define GT_INT_STATUS 0x0c
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#define GT_INT_STATUS_EVENT_FLAG BIT(0)
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#define GT_COMP0 0x10
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#define GT_COMP1 0x14
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#define GT_AUTO_INC 0x18
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/*
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* We are expecting to be clocked by the ARM peripheral clock.
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*
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* Note: it is assumed we are using a prescaler value of zero, so this is
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* the units for all operations.
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*/
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static void __iomem *gt_base;
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static unsigned long gt_clk_rate;
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static int gt_ppi;
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static struct clock_event_device __percpu *gt_evt;
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/*
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* To get the value from the Global Timer Counter register proceed as follows:
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* 1. Read the upper 32-bit timer counter register
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* 2. Read the lower 32-bit timer counter register
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* 3. Read the upper 32-bit timer counter register again. If the value is
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* different to the 32-bit upper value read previously, go back to step 2.
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* Otherwise the 64-bit timer counter value is correct.
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*/
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static u64 notrace _gt_counter_read(void)
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{
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u64 counter;
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u32 lower;
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u32 upper, old_upper;
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upper = readl_relaxed(gt_base + GT_COUNTER1);
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do {
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old_upper = upper;
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lower = readl_relaxed(gt_base + GT_COUNTER0);
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upper = readl_relaxed(gt_base + GT_COUNTER1);
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} while (upper != old_upper);
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counter = upper;
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counter <<= 32;
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counter |= lower;
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return counter;
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}
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static u64 gt_counter_read(void)
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{
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return _gt_counter_read();
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}
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/**
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* To ensure that updates to comparator value register do not set the
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* Interrupt Status Register proceed as follows:
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* 1. Clear the Comp Enable bit in the Timer Control Register.
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* 2. Write the lower 32-bit Comparator Value Register.
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* 3. Write the upper 32-bit Comparator Value Register.
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* 4. Set the Comp Enable bit and, if necessary, the IRQ enable bit.
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*/
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static void gt_compare_set(unsigned long delta, int periodic)
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{
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u64 counter = gt_counter_read();
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unsigned long ctrl;
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counter += delta;
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ctrl = GT_CONTROL_TIMER_ENABLE;
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writel_relaxed(ctrl, gt_base + GT_CONTROL);
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writel_relaxed(lower_32_bits(counter), gt_base + GT_COMP0);
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writel_relaxed(upper_32_bits(counter), gt_base + GT_COMP1);
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if (periodic) {
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writel_relaxed(delta, gt_base + GT_AUTO_INC);
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ctrl |= GT_CONTROL_AUTO_INC;
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}
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ctrl |= GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE;
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writel_relaxed(ctrl, gt_base + GT_CONTROL);
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}
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static int gt_clockevent_shutdown(struct clock_event_device *evt)
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{
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unsigned long ctrl;
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ctrl = readl(gt_base + GT_CONTROL);
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ctrl &= ~(GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE |
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GT_CONTROL_AUTO_INC);
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writel(ctrl, gt_base + GT_CONTROL);
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return 0;
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}
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static int gt_clockevent_set_periodic(struct clock_event_device *evt)
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{
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gt_compare_set(DIV_ROUND_CLOSEST(gt_clk_rate, HZ), 1);
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return 0;
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}
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static int gt_clockevent_set_next_event(unsigned long evt,
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struct clock_event_device *unused)
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{
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gt_compare_set(evt, 0);
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return 0;
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}
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static irqreturn_t gt_clockevent_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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if (!(readl_relaxed(gt_base + GT_INT_STATUS) &
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GT_INT_STATUS_EVENT_FLAG))
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return IRQ_NONE;
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/**
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* ERRATA 740657( Global Timer can send 2 interrupts for
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* the same event in single-shot mode)
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* Workaround:
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* Either disable single-shot mode.
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* Or
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* Modify the Interrupt Handler to avoid the
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* offending sequence. This is achieved by clearing
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* the Global Timer flag _after_ having incremented
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* the Comparator register value to a higher value.
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*/
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if (clockevent_state_oneshot(evt))
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gt_compare_set(ULONG_MAX, 0);
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writel_relaxed(GT_INT_STATUS_EVENT_FLAG, gt_base + GT_INT_STATUS);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static int gt_starting_cpu(unsigned int cpu)
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{
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struct clock_event_device *clk = this_cpu_ptr(gt_evt);
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clk->name = "arm_global_timer";
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clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
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CLOCK_EVT_FEAT_PERCPU;
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clk->set_state_shutdown = gt_clockevent_shutdown;
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clk->set_state_periodic = gt_clockevent_set_periodic;
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clk->set_state_oneshot = gt_clockevent_shutdown;
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clk->set_state_oneshot_stopped = gt_clockevent_shutdown;
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clk->set_next_event = gt_clockevent_set_next_event;
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clk->cpumask = cpumask_of(cpu);
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clk->rating = 300;
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clk->irq = gt_ppi;
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clockevents_config_and_register(clk, gt_clk_rate,
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1, 0xffffffff);
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enable_percpu_irq(clk->irq, IRQ_TYPE_NONE);
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return 0;
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}
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static int gt_dying_cpu(unsigned int cpu)
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{
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struct clock_event_device *clk = this_cpu_ptr(gt_evt);
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gt_clockevent_shutdown(clk);
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disable_percpu_irq(clk->irq);
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return 0;
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}
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static u64 gt_clocksource_read(struct clocksource *cs)
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{
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return gt_counter_read();
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}
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static void gt_resume(struct clocksource *cs)
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{
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unsigned long ctrl;
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ctrl = readl(gt_base + GT_CONTROL);
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if (!(ctrl & GT_CONTROL_TIMER_ENABLE))
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/* re-enable timer on resume */
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writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
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}
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static struct clocksource gt_clocksource = {
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.name = "arm_global_timer",
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.rating = 300,
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.read = gt_clocksource_read,
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.mask = CLOCKSOURCE_MASK(64),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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.resume = gt_resume,
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};
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#ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
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static u64 notrace gt_sched_clock_read(void)
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{
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return _gt_counter_read();
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}
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#endif
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static unsigned long gt_read_long(void)
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{
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return readl_relaxed(gt_base + GT_COUNTER0);
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}
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static struct delay_timer gt_delay_timer = {
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.read_current_timer = gt_read_long,
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};
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static void __init gt_delay_timer_init(void)
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{
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gt_delay_timer.freq = gt_clk_rate;
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register_current_timer_delay(>_delay_timer);
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}
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static int __init gt_clocksource_init(void)
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{
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writel(0, gt_base + GT_CONTROL);
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writel(0, gt_base + GT_COUNTER0);
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writel(0, gt_base + GT_COUNTER1);
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/* enables timer on all the cores */
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writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
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#ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
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sched_clock_register(gt_sched_clock_read, 64, gt_clk_rate);
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#endif
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return clocksource_register_hz(>_clocksource, gt_clk_rate);
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}
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static int __init global_timer_of_register(struct device_node *np)
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{
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struct clk *gt_clk;
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int err = 0;
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/*
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* In A9 r2p0 the comparators for each processor with the global timer
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* fire when the timer value is greater than or equal to. In previous
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* revisions the comparators fired when the timer value was equal to.
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*/
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9
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&& (read_cpuid_id() & 0xf0000f) < 0x200000) {
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pr_warn("global-timer: non support for this cpu version.\n");
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return -ENOSYS;
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}
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gt_ppi = irq_of_parse_and_map(np, 0);
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if (!gt_ppi) {
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pr_warn("global-timer: unable to parse irq\n");
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return -EINVAL;
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}
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gt_base = of_iomap(np, 0);
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if (!gt_base) {
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pr_warn("global-timer: invalid base address\n");
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return -ENXIO;
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}
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gt_clk = of_clk_get(np, 0);
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if (!IS_ERR(gt_clk)) {
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err = clk_prepare_enable(gt_clk);
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if (err)
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goto out_unmap;
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} else {
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pr_warn("global-timer: clk not found\n");
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err = -EINVAL;
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goto out_unmap;
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}
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gt_clk_rate = clk_get_rate(gt_clk);
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gt_evt = alloc_percpu(struct clock_event_device);
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if (!gt_evt) {
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pr_warn("global-timer: can't allocate memory\n");
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err = -ENOMEM;
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goto out_clk;
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}
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err = request_percpu_irq(gt_ppi, gt_clockevent_interrupt,
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"gt", gt_evt);
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if (err) {
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pr_warn("global-timer: can't register interrupt %d (%d)\n",
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gt_ppi, err);
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goto out_free;
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}
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/* Register and immediately configure the timer on the boot CPU */
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err = gt_clocksource_init();
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if (err)
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goto out_irq;
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err = cpuhp_setup_state(CPUHP_AP_ARM_GLOBAL_TIMER_STARTING,
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"clockevents/arm/global_timer:starting",
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gt_starting_cpu, gt_dying_cpu);
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if (err)
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goto out_irq;
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gt_delay_timer_init();
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return 0;
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out_irq:
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free_percpu_irq(gt_ppi, gt_evt);
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out_free:
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free_percpu(gt_evt);
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out_clk:
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clk_disable_unprepare(gt_clk);
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out_unmap:
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iounmap(gt_base);
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WARN(err, "ARM Global timer register failed (%d)\n", err);
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return err;
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}
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/* Only tested on r2p2 and r3p0 */
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TIMER_OF_DECLARE(arm_gt, "arm,cortex-a9-global-timer",
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global_timer_of_register);
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