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77deb66d26
Add helper functions for the translation between parent index and register value in the generic multiplexer function. The purpose of this change is avoid duplicating the code in other clock providers, using the same generic logic. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
252 lines
5.8 KiB
C
252 lines
5.8 KiB
C
/*
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* Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
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* Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
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* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Simple multiplexer clock implementation
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/err.h>
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/*
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* DOC: basic adjustable multiplexer clock that cannot gate
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*
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* Traits of this clock:
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* prepare - clk_prepare only ensures that parents are prepared
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* enable - clk_enable only ensures that parents are enabled
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* rate - rate is only affected by parent switching. No clk_set_rate support
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* parent - parent is adjustable through clk_set_parent
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*/
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int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
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unsigned int val)
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{
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int num_parents = clk_hw_get_num_parents(hw);
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if (table) {
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int i;
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for (i = 0; i < num_parents; i++)
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if (table[i] == val)
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return i;
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return -EINVAL;
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}
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if (val && (flags & CLK_MUX_INDEX_BIT))
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val = ffs(val) - 1;
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if (val && (flags & CLK_MUX_INDEX_ONE))
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val--;
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if (val >= num_parents)
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return -EINVAL;
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return val;
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}
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EXPORT_SYMBOL_GPL(clk_mux_val_to_index);
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unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index)
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{
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unsigned int val = index;
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if (table) {
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val = table[index];
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} else {
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if (flags & CLK_MUX_INDEX_BIT)
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val = 1 << index;
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if (flags & CLK_MUX_INDEX_ONE)
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val++;
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}
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return val;
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}
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EXPORT_SYMBOL_GPL(clk_mux_index_to_val);
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static u8 clk_mux_get_parent(struct clk_hw *hw)
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{
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struct clk_mux *mux = to_clk_mux(hw);
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u32 val;
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val = clk_readl(mux->reg) >> mux->shift;
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val &= mux->mask;
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return clk_mux_val_to_index(hw, mux->table, mux->flags, val);
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}
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static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_mux *mux = to_clk_mux(hw);
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u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
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unsigned long flags = 0;
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u32 reg;
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if (mux->lock)
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spin_lock_irqsave(mux->lock, flags);
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else
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__acquire(mux->lock);
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if (mux->flags & CLK_MUX_HIWORD_MASK) {
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reg = mux->mask << (mux->shift + 16);
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} else {
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reg = clk_readl(mux->reg);
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reg &= ~(mux->mask << mux->shift);
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}
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val = val << mux->shift;
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reg |= val;
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clk_writel(reg, mux->reg);
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if (mux->lock)
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spin_unlock_irqrestore(mux->lock, flags);
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else
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__release(mux->lock);
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return 0;
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}
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const struct clk_ops clk_mux_ops = {
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.get_parent = clk_mux_get_parent,
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.set_parent = clk_mux_set_parent,
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.determine_rate = __clk_mux_determine_rate,
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};
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EXPORT_SYMBOL_GPL(clk_mux_ops);
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const struct clk_ops clk_mux_ro_ops = {
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.get_parent = clk_mux_get_parent,
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};
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EXPORT_SYMBOL_GPL(clk_mux_ro_ops);
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struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
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const char * const *parent_names, u8 num_parents,
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unsigned long flags,
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void __iomem *reg, u8 shift, u32 mask,
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u8 clk_mux_flags, u32 *table, spinlock_t *lock)
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{
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struct clk_mux *mux;
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struct clk_hw *hw;
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struct clk_init_data init;
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u8 width = 0;
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int ret;
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if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
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width = fls(mask) - ffs(mask) + 1;
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if (width + shift > 16) {
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pr_err("mux value exceeds LOWORD field\n");
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return ERR_PTR(-EINVAL);
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}
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}
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/* allocate the mux */
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mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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if (!mux)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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if (clk_mux_flags & CLK_MUX_READ_ONLY)
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init.ops = &clk_mux_ro_ops;
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else
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init.ops = &clk_mux_ops;
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init.flags = flags | CLK_IS_BASIC;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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/* struct clk_mux assignments */
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mux->reg = reg;
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mux->shift = shift;
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mux->mask = mask;
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mux->flags = clk_mux_flags;
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mux->lock = lock;
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mux->table = table;
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mux->hw.init = &init;
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hw = &mux->hw;
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ret = clk_hw_register(dev, hw);
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if (ret) {
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kfree(mux);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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EXPORT_SYMBOL_GPL(clk_hw_register_mux_table);
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struct clk *clk_register_mux_table(struct device *dev, const char *name,
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const char * const *parent_names, u8 num_parents,
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unsigned long flags,
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void __iomem *reg, u8 shift, u32 mask,
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u8 clk_mux_flags, u32 *table, spinlock_t *lock)
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{
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struct clk_hw *hw;
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hw = clk_hw_register_mux_table(dev, name, parent_names, num_parents,
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flags, reg, shift, mask, clk_mux_flags,
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table, lock);
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if (IS_ERR(hw))
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return ERR_CAST(hw);
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return hw->clk;
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}
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EXPORT_SYMBOL_GPL(clk_register_mux_table);
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struct clk *clk_register_mux(struct device *dev, const char *name,
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const char * const *parent_names, u8 num_parents,
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unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_mux_flags, spinlock_t *lock)
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{
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u32 mask = BIT(width) - 1;
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return clk_register_mux_table(dev, name, parent_names, num_parents,
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flags, reg, shift, mask, clk_mux_flags,
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NULL, lock);
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}
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EXPORT_SYMBOL_GPL(clk_register_mux);
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struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name,
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const char * const *parent_names, u8 num_parents,
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unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_mux_flags, spinlock_t *lock)
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{
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u32 mask = BIT(width) - 1;
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return clk_hw_register_mux_table(dev, name, parent_names, num_parents,
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flags, reg, shift, mask, clk_mux_flags,
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NULL, lock);
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}
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EXPORT_SYMBOL_GPL(clk_hw_register_mux);
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void clk_unregister_mux(struct clk *clk)
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{
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struct clk_mux *mux;
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struct clk_hw *hw;
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hw = __clk_get_hw(clk);
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if (!hw)
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return;
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mux = to_clk_mux(hw);
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clk_unregister(clk);
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kfree(mux);
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}
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EXPORT_SYMBOL_GPL(clk_unregister_mux);
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void clk_hw_unregister_mux(struct clk_hw *hw)
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{
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struct clk_mux *mux;
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mux = to_clk_mux(hw);
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clk_hw_unregister(hw);
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kfree(mux);
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}
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EXPORT_SYMBOL_GPL(clk_hw_unregister_mux);
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