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8a53fc511c
According to the Aspeed specification, the reset and enable sequence
should be done when the clock is stopped. The specification doesn't
define behavior if the reset is done while the clock is enabled.
From testing on the AST2500, the LPC Controller has problems if the
clock is reset while enabled.
Therefore, check whether the clock is enabled or not before performing
the reset and enable sequence in the Aspeed clock driver.
Reported-by: Lei Yu <mine260309@gmail.com>
Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com>
Fixes: 15ed8ce5f8
("clk: aspeed: Register gated clocks")
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
674 lines
18 KiB
C
674 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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#define pr_fmt(fmt) "clk-aspeed: " fmt
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#include <linux/clk-provider.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset-controller.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <dt-bindings/clock/aspeed-clock.h>
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#define ASPEED_NUM_CLKS 35
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#define ASPEED_RESET_CTRL 0x04
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#define ASPEED_CLK_SELECTION 0x08
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#define ASPEED_CLK_STOP_CTRL 0x0c
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#define ASPEED_MPLL_PARAM 0x20
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#define ASPEED_HPLL_PARAM 0x24
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#define AST2500_HPLL_BYPASS_EN BIT(20)
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#define AST2400_HPLL_STRAPPED BIT(18)
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#define AST2400_HPLL_BYPASS_EN BIT(17)
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#define ASPEED_MISC_CTRL 0x2c
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#define UART_DIV13_EN BIT(12)
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#define ASPEED_STRAP 0x70
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#define CLKIN_25MHZ_EN BIT(23)
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#define AST2400_CLK_SOURCE_SEL BIT(18)
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#define ASPEED_CLK_SELECTION_2 0xd8
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/* Globally visible clocks */
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static DEFINE_SPINLOCK(aspeed_clk_lock);
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/* Keeps track of all clocks */
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static struct clk_hw_onecell_data *aspeed_clk_data;
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static void __iomem *scu_base;
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/**
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* struct aspeed_gate_data - Aspeed gated clocks
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* @clock_idx: bit used to gate this clock in the clock register
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* @reset_idx: bit used to reset this IP in the reset register. -1 if no
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* reset is required when enabling the clock
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* @name: the clock name
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* @parent_name: the name of the parent clock
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* @flags: standard clock framework flags
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*/
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struct aspeed_gate_data {
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u8 clock_idx;
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s8 reset_idx;
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const char *name;
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const char *parent_name;
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unsigned long flags;
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};
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/**
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* struct aspeed_clk_gate - Aspeed specific clk_gate structure
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* @hw: handle between common and hardware-specific interfaces
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* @reg: register controlling gate
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* @clock_idx: bit used to gate this clock in the clock register
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* @reset_idx: bit used to reset this IP in the reset register. -1 if no
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* reset is required when enabling the clock
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* @flags: hardware-specific flags
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* @lock: register lock
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*
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* Some of the clocks in the Aspeed SoC must be put in reset before enabling.
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* This modified version of clk_gate allows an optional reset bit to be
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* specified.
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*/
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struct aspeed_clk_gate {
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struct clk_hw hw;
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struct regmap *map;
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u8 clock_idx;
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s8 reset_idx;
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u8 flags;
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spinlock_t *lock;
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};
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#define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw)
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/* TODO: ask Aspeed about the actual parent data */
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static const struct aspeed_gate_data aspeed_gates[] = {
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/* clk rst name parent flags */
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[ASPEED_CLK_GATE_ECLK] = { 0, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */
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[ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
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[ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
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[ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */
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[ASPEED_CLK_GATE_BCLK] = { 4, 10, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */
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[ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, 0 }, /* DAC */
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[ASPEED_CLK_GATE_REFCLK] = { 6, -1, "refclk-gate", "clkin", CLK_IS_CRITICAL },
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[ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */
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[ASPEED_CLK_GATE_LCLK] = { 8, 5, "lclk-gate", NULL, 0 }, /* LPC */
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[ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */
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[ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", NULL, 0 }, /* GFX CRT */
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[ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */
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[ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */
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[ASPEED_CLK_GATE_UART1CLK] = { 15, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */
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[ASPEED_CLK_GATE_UART2CLK] = { 16, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */
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[ASPEED_CLK_GATE_UART5CLK] = { 17, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */
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[ASPEED_CLK_GATE_ESPICLK] = { 19, -1, "espiclk-gate", NULL, 0 }, /* eSPI */
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[ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac", 0 }, /* MAC1 */
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[ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac", 0 }, /* MAC2 */
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[ASPEED_CLK_GATE_RSACLK] = { 24, -1, "rsaclk-gate", NULL, 0 }, /* RSA */
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[ASPEED_CLK_GATE_UART3CLK] = { 25, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
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[ASPEED_CLK_GATE_UART4CLK] = { 26, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */
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[ASPEED_CLK_GATE_SDCLKCLK] = { 27, 16, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
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[ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
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};
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static const struct clk_div_table ast2500_mac_div_table[] = {
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{ 0x0, 4 }, /* Yep, really. Aspeed confirmed this is correct */
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{ 0x1, 4 },
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{ 0x2, 6 },
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{ 0x3, 8 },
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{ 0x4, 10 },
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{ 0x5, 12 },
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{ 0x6, 14 },
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{ 0x7, 16 },
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{ 0 }
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};
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static const struct clk_div_table ast2400_div_table[] = {
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{ 0x0, 2 },
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{ 0x1, 4 },
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{ 0x2, 6 },
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{ 0x3, 8 },
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{ 0x4, 10 },
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{ 0x5, 12 },
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{ 0x6, 14 },
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{ 0x7, 16 },
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{ 0 }
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};
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static const struct clk_div_table ast2500_div_table[] = {
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{ 0x0, 4 },
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{ 0x1, 8 },
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{ 0x2, 12 },
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{ 0x3, 16 },
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{ 0x4, 20 },
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{ 0x5, 24 },
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{ 0x6, 28 },
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{ 0x7, 32 },
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{ 0 }
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};
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static struct clk_hw *aspeed_ast2400_calc_pll(const char *name, u32 val)
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{
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unsigned int mult, div;
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if (val & AST2400_HPLL_BYPASS_EN) {
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/* Pass through mode */
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mult = div = 1;
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} else {
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/* F = 24Mhz * (2-OD) * [(N + 2) / (D + 1)] */
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u32 n = (val >> 5) & 0x3f;
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u32 od = (val >> 4) & 0x1;
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u32 d = val & 0xf;
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mult = (2 - od) * (n + 2);
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div = d + 1;
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}
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return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
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mult, div);
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};
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static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val)
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{
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unsigned int mult, div;
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if (val & AST2500_HPLL_BYPASS_EN) {
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/* Pass through mode */
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mult = div = 1;
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} else {
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/* F = clkin * [(M+1) / (N+1)] / (P + 1) */
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u32 p = (val >> 13) & 0x3f;
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u32 m = (val >> 5) & 0xff;
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u32 n = val & 0x1f;
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mult = (m + 1) / (n + 1);
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div = p + 1;
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}
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return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
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mult, div);
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}
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struct aspeed_clk_soc_data {
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const struct clk_div_table *div_table;
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const struct clk_div_table *mac_div_table;
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struct clk_hw *(*calc_pll)(const char *name, u32 val);
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};
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static const struct aspeed_clk_soc_data ast2500_data = {
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.div_table = ast2500_div_table,
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.mac_div_table = ast2500_mac_div_table,
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.calc_pll = aspeed_ast2500_calc_pll,
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};
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static const struct aspeed_clk_soc_data ast2400_data = {
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.div_table = ast2400_div_table,
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.mac_div_table = ast2400_div_table,
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.calc_pll = aspeed_ast2400_calc_pll,
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};
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static int aspeed_clk_is_enabled(struct clk_hw *hw)
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{
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struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
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u32 clk = BIT(gate->clock_idx);
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u32 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
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u32 reg;
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regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, ®);
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return ((reg & clk) == enval) ? 1 : 0;
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}
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static int aspeed_clk_enable(struct clk_hw *hw)
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{
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struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
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unsigned long flags;
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u32 clk = BIT(gate->clock_idx);
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u32 rst = BIT(gate->reset_idx);
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u32 enval;
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spin_lock_irqsave(gate->lock, flags);
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if (aspeed_clk_is_enabled(hw)) {
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spin_unlock_irqrestore(gate->lock, flags);
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return 0;
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}
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if (gate->reset_idx >= 0) {
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/* Put IP in reset */
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regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, rst);
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/* Delay 100us */
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udelay(100);
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}
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/* Enable clock */
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enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
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regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, enval);
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if (gate->reset_idx >= 0) {
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/* A delay of 10ms is specified by the ASPEED docs */
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mdelay(10);
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/* Take IP out of reset */
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regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, 0);
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}
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spin_unlock_irqrestore(gate->lock, flags);
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return 0;
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}
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static void aspeed_clk_disable(struct clk_hw *hw)
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{
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struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
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unsigned long flags;
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u32 clk = BIT(gate->clock_idx);
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u32 enval;
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spin_lock_irqsave(gate->lock, flags);
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enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? clk : 0;
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regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, enval);
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spin_unlock_irqrestore(gate->lock, flags);
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}
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static const struct clk_ops aspeed_clk_gate_ops = {
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.enable = aspeed_clk_enable,
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.disable = aspeed_clk_disable,
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.is_enabled = aspeed_clk_is_enabled,
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};
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/**
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* struct aspeed_reset - Aspeed reset controller
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* @map: regmap to access the containing system controller
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* @rcdev: reset controller device
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*/
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struct aspeed_reset {
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struct regmap *map;
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struct reset_controller_dev rcdev;
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};
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#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)
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static const u8 aspeed_resets[] = {
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[ASPEED_RESET_XDMA] = 25,
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[ASPEED_RESET_MCTP] = 24,
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[ASPEED_RESET_ADC] = 23,
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[ASPEED_RESET_JTAG_MASTER] = 22,
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[ASPEED_RESET_MIC] = 18,
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[ASPEED_RESET_PWM] = 9,
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[ASPEED_RESET_PCIVGA] = 8,
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[ASPEED_RESET_I2C] = 2,
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[ASPEED_RESET_AHB] = 1,
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};
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static int aspeed_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct aspeed_reset *ar = to_aspeed_reset(rcdev);
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u32 rst = BIT(aspeed_resets[id]);
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return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, 0);
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}
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static int aspeed_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct aspeed_reset *ar = to_aspeed_reset(rcdev);
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u32 rst = BIT(aspeed_resets[id]);
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return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, rst);
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}
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static int aspeed_reset_status(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct aspeed_reset *ar = to_aspeed_reset(rcdev);
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u32 val, rst = BIT(aspeed_resets[id]);
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int ret;
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ret = regmap_read(ar->map, ASPEED_RESET_CTRL, &val);
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if (ret)
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return ret;
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return !!(val & rst);
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}
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static const struct reset_control_ops aspeed_reset_ops = {
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.assert = aspeed_reset_assert,
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.deassert = aspeed_reset_deassert,
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.status = aspeed_reset_status,
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};
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static struct clk_hw *aspeed_clk_hw_register_gate(struct device *dev,
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const char *name, const char *parent_name, unsigned long flags,
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struct regmap *map, u8 clock_idx, u8 reset_idx,
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u8 clk_gate_flags, spinlock_t *lock)
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{
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struct aspeed_clk_gate *gate;
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struct clk_init_data init;
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struct clk_hw *hw;
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int ret;
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &aspeed_clk_gate_ops;
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init.flags = flags;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.num_parents = parent_name ? 1 : 0;
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gate->map = map;
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gate->clock_idx = clock_idx;
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gate->reset_idx = reset_idx;
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gate->flags = clk_gate_flags;
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gate->lock = lock;
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gate->hw.init = &init;
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hw = &gate->hw;
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ret = clk_hw_register(dev, hw);
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if (ret) {
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kfree(gate);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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static int aspeed_clk_probe(struct platform_device *pdev)
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{
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const struct aspeed_clk_soc_data *soc_data;
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struct device *dev = &pdev->dev;
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struct aspeed_reset *ar;
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struct regmap *map;
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struct clk_hw *hw;
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u32 val, rate;
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int i, ret;
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map = syscon_node_to_regmap(dev->of_node);
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if (IS_ERR(map)) {
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dev_err(dev, "no syscon regmap\n");
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return PTR_ERR(map);
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}
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ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL);
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if (!ar)
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return -ENOMEM;
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ar->map = map;
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ar->rcdev.owner = THIS_MODULE;
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ar->rcdev.nr_resets = ARRAY_SIZE(aspeed_resets);
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ar->rcdev.ops = &aspeed_reset_ops;
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ar->rcdev.of_node = dev->of_node;
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ret = devm_reset_controller_register(dev, &ar->rcdev);
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if (ret) {
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dev_err(dev, "could not register reset controller\n");
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return ret;
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}
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/* SoC generations share common layouts but have different divisors */
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soc_data = of_device_get_match_data(dev);
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if (!soc_data) {
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dev_err(dev, "no match data for platform\n");
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return -EINVAL;
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}
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/* UART clock div13 setting */
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regmap_read(map, ASPEED_MISC_CTRL, &val);
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if (val & UART_DIV13_EN)
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rate = 24000000 / 13;
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else
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rate = 24000000;
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/* TODO: Find the parent data for the uart clock */
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hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate);
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if (IS_ERR(hw))
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return PTR_ERR(hw);
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aspeed_clk_data->hws[ASPEED_CLK_UART] = hw;
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/*
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* Memory controller (M-PLL) PLL. This clock is configured by the
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* bootloader, and is exposed to Linux as a read-only clock rate.
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*/
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regmap_read(map, ASPEED_MPLL_PARAM, &val);
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hw = soc_data->calc_pll("mpll", val);
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if (IS_ERR(hw))
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return PTR_ERR(hw);
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aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw;
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/* SD/SDIO clock divider (TODO: There's a gate too) */
|
|
hw = clk_hw_register_divider_table(dev, "sdio", "hpll", 0,
|
|
scu_base + ASPEED_CLK_SELECTION, 12, 3, 0,
|
|
soc_data->div_table,
|
|
&aspeed_clk_lock);
|
|
if (IS_ERR(hw))
|
|
return PTR_ERR(hw);
|
|
aspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw;
|
|
|
|
/* MAC AHB bus clock divider */
|
|
hw = clk_hw_register_divider_table(dev, "mac", "hpll", 0,
|
|
scu_base + ASPEED_CLK_SELECTION, 16, 3, 0,
|
|
soc_data->mac_div_table,
|
|
&aspeed_clk_lock);
|
|
if (IS_ERR(hw))
|
|
return PTR_ERR(hw);
|
|
aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw;
|
|
|
|
/* LPC Host (LHCLK) clock divider */
|
|
hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
|
|
scu_base + ASPEED_CLK_SELECTION, 20, 3, 0,
|
|
soc_data->div_table,
|
|
&aspeed_clk_lock);
|
|
if (IS_ERR(hw))
|
|
return PTR_ERR(hw);
|
|
aspeed_clk_data->hws[ASPEED_CLK_LHCLK] = hw;
|
|
|
|
/* P-Bus (BCLK) clock divider */
|
|
hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0,
|
|
scu_base + ASPEED_CLK_SELECTION_2, 0, 2, 0,
|
|
soc_data->div_table,
|
|
&aspeed_clk_lock);
|
|
if (IS_ERR(hw))
|
|
return PTR_ERR(hw);
|
|
aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw;
|
|
|
|
/*
|
|
* TODO: There are a number of clocks that not included in this driver
|
|
* as more information is required:
|
|
* D2-PLL
|
|
* D-PLL
|
|
* YCLK
|
|
* RGMII
|
|
* RMII
|
|
* UART[1..5] clock source mux
|
|
* Video Engine (ECLK) mux and clock divider
|
|
*/
|
|
|
|
for (i = 0; i < ARRAY_SIZE(aspeed_gates); i++) {
|
|
const struct aspeed_gate_data *gd = &aspeed_gates[i];
|
|
u32 gate_flags;
|
|
|
|
/* Special case: the USB port 1 clock (bit 14) is always
|
|
* working the opposite way from the other ones.
|
|
*/
|
|
gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE;
|
|
hw = aspeed_clk_hw_register_gate(dev,
|
|
gd->name,
|
|
gd->parent_name,
|
|
gd->flags,
|
|
map,
|
|
gd->clock_idx,
|
|
gd->reset_idx,
|
|
gate_flags,
|
|
&aspeed_clk_lock);
|
|
if (IS_ERR(hw))
|
|
return PTR_ERR(hw);
|
|
aspeed_clk_data->hws[i] = hw;
|
|
}
|
|
|
|
return 0;
|
|
};
|
|
|
|
static const struct of_device_id aspeed_clk_dt_ids[] = {
|
|
{ .compatible = "aspeed,ast2400-scu", .data = &ast2400_data },
|
|
{ .compatible = "aspeed,ast2500-scu", .data = &ast2500_data },
|
|
{ }
|
|
};
|
|
|
|
static struct platform_driver aspeed_clk_driver = {
|
|
.probe = aspeed_clk_probe,
|
|
.driver = {
|
|
.name = "aspeed-clk",
|
|
.of_match_table = aspeed_clk_dt_ids,
|
|
.suppress_bind_attrs = true,
|
|
},
|
|
};
|
|
builtin_platform_driver(aspeed_clk_driver);
|
|
|
|
static void __init aspeed_ast2400_cc(struct regmap *map)
|
|
{
|
|
struct clk_hw *hw;
|
|
u32 val, freq, div;
|
|
|
|
/*
|
|
* CLKIN is the crystal oscillator, 24, 48 or 25MHz selected by
|
|
* strapping
|
|
*/
|
|
regmap_read(map, ASPEED_STRAP, &val);
|
|
if (val & CLKIN_25MHZ_EN)
|
|
freq = 25000000;
|
|
else if (val & AST2400_CLK_SOURCE_SEL)
|
|
freq = 48000000;
|
|
else
|
|
freq = 24000000;
|
|
hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq);
|
|
pr_debug("clkin @%u MHz\n", freq / 1000000);
|
|
|
|
/*
|
|
* High-speed PLL clock derived from the crystal. This the CPU clock,
|
|
* and we assume that it is enabled
|
|
*/
|
|
regmap_read(map, ASPEED_HPLL_PARAM, &val);
|
|
WARN(val & AST2400_HPLL_STRAPPED, "hpll is strapped not configured");
|
|
aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2400_calc_pll("hpll", val);
|
|
|
|
/*
|
|
* Strap bits 11:10 define the CPU/AHB clock frequency ratio (aka HCLK)
|
|
* 00: Select CPU:AHB = 1:1
|
|
* 01: Select CPU:AHB = 2:1
|
|
* 10: Select CPU:AHB = 4:1
|
|
* 11: Select CPU:AHB = 3:1
|
|
*/
|
|
regmap_read(map, ASPEED_STRAP, &val);
|
|
val = (val >> 10) & 0x3;
|
|
div = val + 1;
|
|
if (div == 3)
|
|
div = 4;
|
|
else if (div == 4)
|
|
div = 3;
|
|
hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div);
|
|
aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw;
|
|
|
|
/* APB clock clock selection register SCU08 (aka PCLK) */
|
|
hw = clk_hw_register_divider_table(NULL, "apb", "hpll", 0,
|
|
scu_base + ASPEED_CLK_SELECTION, 23, 3, 0,
|
|
ast2400_div_table,
|
|
&aspeed_clk_lock);
|
|
aspeed_clk_data->hws[ASPEED_CLK_APB] = hw;
|
|
}
|
|
|
|
static void __init aspeed_ast2500_cc(struct regmap *map)
|
|
{
|
|
struct clk_hw *hw;
|
|
u32 val, freq, div;
|
|
|
|
/* CLKIN is the crystal oscillator, 24 or 25MHz selected by strapping */
|
|
regmap_read(map, ASPEED_STRAP, &val);
|
|
if (val & CLKIN_25MHZ_EN)
|
|
freq = 25000000;
|
|
else
|
|
freq = 24000000;
|
|
hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq);
|
|
pr_debug("clkin @%u MHz\n", freq / 1000000);
|
|
|
|
/*
|
|
* High-speed PLL clock derived from the crystal. This the CPU clock,
|
|
* and we assume that it is enabled
|
|
*/
|
|
regmap_read(map, ASPEED_HPLL_PARAM, &val);
|
|
aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2500_calc_pll("hpll", val);
|
|
|
|
/* Strap bits 11:9 define the AXI/AHB clock frequency ratio (aka HCLK)*/
|
|
regmap_read(map, ASPEED_STRAP, &val);
|
|
val = (val >> 9) & 0x7;
|
|
WARN(val == 0, "strapping is zero: cannot determine ahb clock");
|
|
div = 2 * (val + 1);
|
|
hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div);
|
|
aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw;
|
|
|
|
/* APB clock clock selection register SCU08 (aka PCLK) */
|
|
regmap_read(map, ASPEED_CLK_SELECTION, &val);
|
|
val = (val >> 23) & 0x7;
|
|
div = 4 * (val + 1);
|
|
hw = clk_hw_register_fixed_factor(NULL, "apb", "hpll", 0, 1, div);
|
|
aspeed_clk_data->hws[ASPEED_CLK_APB] = hw;
|
|
};
|
|
|
|
static void __init aspeed_cc_init(struct device_node *np)
|
|
{
|
|
struct regmap *map;
|
|
u32 val;
|
|
int ret;
|
|
int i;
|
|
|
|
scu_base = of_iomap(np, 0);
|
|
if (!scu_base)
|
|
return;
|
|
|
|
aspeed_clk_data = kzalloc(sizeof(*aspeed_clk_data) +
|
|
sizeof(*aspeed_clk_data->hws) * ASPEED_NUM_CLKS,
|
|
GFP_KERNEL);
|
|
if (!aspeed_clk_data)
|
|
return;
|
|
|
|
/*
|
|
* This way all clocks fetched before the platform device probes,
|
|
* except those we assign here for early use, will be deferred.
|
|
*/
|
|
for (i = 0; i < ASPEED_NUM_CLKS; i++)
|
|
aspeed_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
|
|
|
|
map = syscon_node_to_regmap(np);
|
|
if (IS_ERR(map)) {
|
|
pr_err("no syscon regmap\n");
|
|
return;
|
|
}
|
|
/*
|
|
* We check that the regmap works on this very first access,
|
|
* but as this is an MMIO-backed regmap, subsequent regmap
|
|
* access is not going to fail and we skip error checks from
|
|
* this point.
|
|
*/
|
|
ret = regmap_read(map, ASPEED_STRAP, &val);
|
|
if (ret) {
|
|
pr_err("failed to read strapping register\n");
|
|
return;
|
|
}
|
|
|
|
if (of_device_is_compatible(np, "aspeed,ast2400-scu"))
|
|
aspeed_ast2400_cc(map);
|
|
else if (of_device_is_compatible(np, "aspeed,ast2500-scu"))
|
|
aspeed_ast2500_cc(map);
|
|
else
|
|
pr_err("unknown platform, failed to add clocks\n");
|
|
|
|
aspeed_clk_data->num = ASPEED_NUM_CLKS;
|
|
ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data);
|
|
if (ret)
|
|
pr_err("failed to add DT provider: %d\n", ret);
|
|
};
|
|
CLK_OF_DECLARE_DRIVER(aspeed_cc_g5, "aspeed,ast2500-scu", aspeed_cc_init);
|
|
CLK_OF_DECLARE_DRIVER(aspeed_cc_g4, "aspeed,ast2400-scu", aspeed_cc_init);
|