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219a5859c8
The otgphy clocks really only drive the phy blocks. These in turn contain plls that then generate the 480m clocks the clock controller uses to supply some other clocks like uart0, gpu or the video-codec. So fix this structure to actually respect that hirarchy and removed that usb480m fixed-rate clock working as a placeholder till now, as this wouldn't even work if the supplying phy gets turned off while its pll-output gets used elsewhere. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Douglas Anderson <dianders@chromium.org> Acked-by: Michael Turquette <mturquette@baylibre.com> |
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| .. | ||
| clk-cpu.c | ||
| clk-inverter.c | ||
| clk-mmc-phase.c | ||
| clk-pll.c | ||
| clk-rk3036.c | ||
| clk-rk3188.c | ||
| clk-rk3228.c | ||
| clk-rk3288.c | ||
| clk-rk3368.c | ||
| clk-rockchip.c | ||
| clk.c | ||
| clk.h | ||
| Makefile | ||
| softrst.c | ||