Conor Dooley 6fc655ed49 riscv: dts: microchip: icicle: update pci address properties ... For the v2022.09 reference design the PCI root port's data region has been moved to FIC1 from FIC0. This is a shorter path, allowing for higher clock rates and improved through-put. As a result, the address at which the PCIe's data region appears to the core complex has changed. The config region's address is unchanged. As FIC0 is no longer used, its clock can be removed too. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>		2022-09-27 18:53:58 +01:00
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boot	riscv: dts: microchip: icicle: update pci address properties	2022-09-27 18:53:58 +01:00
configs	riscv: enable Docker requirements in defconfig	2022-07-22 13:43:28 -07:00
errata	riscv: implement Zicbom-based CMO instructions + the t-head variant	2022-08-10 20:49:32 -07:00
include	RISC-V: KVM: Support sstc extension	2022-08-12 07:43:57 -07:00
kernel	RISC-V Patches for the 5.20 Merge Window, Part 2	2022-08-12 18:39:43 -07:00
kvm	RISC-V: KVM: Support sstc extension	2022-08-12 07:43:57 -07:00
lib	riscv: lib: uaccess: fix CSR_STATUS SR_SUM bit	2022-08-10 14:06:31 -07:00
mm	RISC-V: fixups to work with crash tool	2022-08-11 09:04:01 -07:00
net	bpf, riscv: Support riscv jit to provide bpf_line_info	2022-06-02 16:26:01 -07:00
purgatory	riscv/purgatory: Omit use of bin2c	2022-08-11 09:32:34 -07:00
Kbuild	riscv: move errata/ and kvm/ builds to arch/riscv/Kbuild	2022-06-01 22:26:32 -07:00
Kconfig	riscv/purgatory: Omit use of bin2c	2022-08-11 09:32:34 -07:00
Kconfig.debug	RISC-V: Remove EARLY_PRINTK support	2018-12-17 10:23:46 -08:00
Kconfig.erratas	riscv: implement Zicbom-based CMO instructions + the t-head variant	2022-08-10 20:49:32 -07:00
Kconfig.socs	riscv: Kconfig: Style cleanups	2022-06-30 19:26:16 -07:00
Makefile	arch/riscv: add Zihintpause support	2022-08-11 08:03:49 -07:00