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f55956065e
This patch is pretty much a carbon copy of commit3079c65214
("caif: Fix napi poll list corruption") with "caif" replaced by "emac". The commitd75b1ade56
("net: less interrupt masking in NAPI") breaks emac. It is now required that if the entire budget is consumed when poll returns, the napi poll_list must remain empty. However, like some other drivers emac tries to do a last-ditch check and if there is more work it will call napi_reschedule and then immediately process some of this new work. Should the entire budget be consumed while processing such new work then we will violate the new caller contract. This patch fixes this by not touching any work when we reschedule in emac. Signed-off-by: Christian Lamparter <chunkeey@googlemail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
788 lines
19 KiB
C
788 lines
19 KiB
C
/*
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* drivers/net/ethernet/ibm/emac/mal.c
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*
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* Memory Access Layer (MAL) support
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*
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* Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
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* <benh@kernel.crashing.org>
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*
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* Based on the arch/ppc version of the driver:
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*
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* Copyright (c) 2004, 2005 Zultys Technologies.
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* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
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*
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* Based on original work by
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* Benjamin Herrenschmidt <benh@kernel.crashing.org>,
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* David Gibson <hermes@gibson.dropbear.id.au>,
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*
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* Armin Kuster <akuster@mvista.com>
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* Copyright 2002 MontaVista Softare Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/of_irq.h>
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#include "core.h"
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#include <asm/dcr-regs.h>
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static int mal_count;
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int mal_register_commac(struct mal_instance *mal, struct mal_commac *commac)
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{
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unsigned long flags;
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spin_lock_irqsave(&mal->lock, flags);
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MAL_DBG(mal, "reg(%08x, %08x)" NL,
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commac->tx_chan_mask, commac->rx_chan_mask);
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/* Don't let multiple commacs claim the same channel(s) */
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if ((mal->tx_chan_mask & commac->tx_chan_mask) ||
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(mal->rx_chan_mask & commac->rx_chan_mask)) {
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spin_unlock_irqrestore(&mal->lock, flags);
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printk(KERN_WARNING "mal%d: COMMAC channels conflict!\n",
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mal->index);
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return -EBUSY;
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}
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if (list_empty(&mal->list))
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napi_enable(&mal->napi);
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mal->tx_chan_mask |= commac->tx_chan_mask;
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mal->rx_chan_mask |= commac->rx_chan_mask;
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list_add(&commac->list, &mal->list);
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spin_unlock_irqrestore(&mal->lock, flags);
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return 0;
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}
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void mal_unregister_commac(struct mal_instance *mal,
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struct mal_commac *commac)
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{
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unsigned long flags;
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spin_lock_irqsave(&mal->lock, flags);
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MAL_DBG(mal, "unreg(%08x, %08x)" NL,
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commac->tx_chan_mask, commac->rx_chan_mask);
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mal->tx_chan_mask &= ~commac->tx_chan_mask;
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mal->rx_chan_mask &= ~commac->rx_chan_mask;
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list_del_init(&commac->list);
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if (list_empty(&mal->list))
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napi_disable(&mal->napi);
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spin_unlock_irqrestore(&mal->lock, flags);
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}
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int mal_set_rcbs(struct mal_instance *mal, int channel, unsigned long size)
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{
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BUG_ON(channel < 0 || channel >= mal->num_rx_chans ||
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size > MAL_MAX_RX_SIZE);
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MAL_DBG(mal, "set_rbcs(%d, %lu)" NL, channel, size);
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if (size & 0xf) {
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printk(KERN_WARNING
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"mal%d: incorrect RX size %lu for the channel %d\n",
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mal->index, size, channel);
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return -EINVAL;
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}
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set_mal_dcrn(mal, MAL_RCBS(channel), size >> 4);
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return 0;
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}
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int mal_tx_bd_offset(struct mal_instance *mal, int channel)
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{
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BUG_ON(channel < 0 || channel >= mal->num_tx_chans);
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return channel * NUM_TX_BUFF;
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}
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int mal_rx_bd_offset(struct mal_instance *mal, int channel)
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{
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BUG_ON(channel < 0 || channel >= mal->num_rx_chans);
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return mal->num_tx_chans * NUM_TX_BUFF + channel * NUM_RX_BUFF;
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}
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void mal_enable_tx_channel(struct mal_instance *mal, int channel)
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{
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unsigned long flags;
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spin_lock_irqsave(&mal->lock, flags);
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MAL_DBG(mal, "enable_tx(%d)" NL, channel);
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set_mal_dcrn(mal, MAL_TXCASR,
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get_mal_dcrn(mal, MAL_TXCASR) | MAL_CHAN_MASK(channel));
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spin_unlock_irqrestore(&mal->lock, flags);
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}
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void mal_disable_tx_channel(struct mal_instance *mal, int channel)
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{
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set_mal_dcrn(mal, MAL_TXCARR, MAL_CHAN_MASK(channel));
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MAL_DBG(mal, "disable_tx(%d)" NL, channel);
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}
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void mal_enable_rx_channel(struct mal_instance *mal, int channel)
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{
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unsigned long flags;
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/*
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* On some 4xx PPC's (e.g. 460EX/GT), the rx channel is a multiple
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* of 8, but enabling in MAL_RXCASR needs the divided by 8 value
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* for the bitmask
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*/
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if (!(channel % 8))
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channel >>= 3;
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spin_lock_irqsave(&mal->lock, flags);
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MAL_DBG(mal, "enable_rx(%d)" NL, channel);
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set_mal_dcrn(mal, MAL_RXCASR,
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get_mal_dcrn(mal, MAL_RXCASR) | MAL_CHAN_MASK(channel));
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spin_unlock_irqrestore(&mal->lock, flags);
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}
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void mal_disable_rx_channel(struct mal_instance *mal, int channel)
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{
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/*
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* On some 4xx PPC's (e.g. 460EX/GT), the rx channel is a multiple
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* of 8, but enabling in MAL_RXCASR needs the divided by 8 value
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* for the bitmask
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*/
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if (!(channel % 8))
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channel >>= 3;
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set_mal_dcrn(mal, MAL_RXCARR, MAL_CHAN_MASK(channel));
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MAL_DBG(mal, "disable_rx(%d)" NL, channel);
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}
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void mal_poll_add(struct mal_instance *mal, struct mal_commac *commac)
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{
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unsigned long flags;
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spin_lock_irqsave(&mal->lock, flags);
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MAL_DBG(mal, "poll_add(%p)" NL, commac);
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/* starts disabled */
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set_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags);
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list_add_tail(&commac->poll_list, &mal->poll_list);
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spin_unlock_irqrestore(&mal->lock, flags);
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}
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void mal_poll_del(struct mal_instance *mal, struct mal_commac *commac)
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{
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unsigned long flags;
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spin_lock_irqsave(&mal->lock, flags);
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MAL_DBG(mal, "poll_del(%p)" NL, commac);
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list_del(&commac->poll_list);
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spin_unlock_irqrestore(&mal->lock, flags);
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}
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/* synchronized by mal_poll() */
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static inline void mal_enable_eob_irq(struct mal_instance *mal)
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{
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MAL_DBG2(mal, "enable_irq" NL);
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// XXX might want to cache MAL_CFG as the DCR read can be slooooow
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set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) | MAL_CFG_EOPIE);
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}
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/* synchronized by NAPI state */
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static inline void mal_disable_eob_irq(struct mal_instance *mal)
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{
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// XXX might want to cache MAL_CFG as the DCR read can be slooooow
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set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) & ~MAL_CFG_EOPIE);
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MAL_DBG2(mal, "disable_irq" NL);
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}
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static irqreturn_t mal_serr(int irq, void *dev_instance)
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{
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struct mal_instance *mal = dev_instance;
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u32 esr = get_mal_dcrn(mal, MAL_ESR);
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/* Clear the error status register */
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set_mal_dcrn(mal, MAL_ESR, esr);
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MAL_DBG(mal, "SERR %08x" NL, esr);
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if (esr & MAL_ESR_EVB) {
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if (esr & MAL_ESR_DE) {
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/* We ignore Descriptor error,
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* TXDE or RXDE interrupt will be generated anyway.
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*/
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return IRQ_HANDLED;
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}
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if (esr & MAL_ESR_PEIN) {
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/* PLB error, it's probably buggy hardware or
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* incorrect physical address in BD (i.e. bug)
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*/
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if (net_ratelimit())
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printk(KERN_ERR
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"mal%d: system error, "
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"PLB (ESR = 0x%08x)\n",
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mal->index, esr);
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return IRQ_HANDLED;
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}
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/* OPB error, it's probably buggy hardware or incorrect
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* EBC setup
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*/
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if (net_ratelimit())
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printk(KERN_ERR
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"mal%d: system error, OPB (ESR = 0x%08x)\n",
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mal->index, esr);
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}
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return IRQ_HANDLED;
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}
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static inline void mal_schedule_poll(struct mal_instance *mal)
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{
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if (likely(napi_schedule_prep(&mal->napi))) {
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MAL_DBG2(mal, "schedule_poll" NL);
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spin_lock(&mal->lock);
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mal_disable_eob_irq(mal);
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spin_unlock(&mal->lock);
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__napi_schedule(&mal->napi);
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} else
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MAL_DBG2(mal, "already in poll" NL);
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}
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static irqreturn_t mal_txeob(int irq, void *dev_instance)
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{
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struct mal_instance *mal = dev_instance;
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u32 r = get_mal_dcrn(mal, MAL_TXEOBISR);
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MAL_DBG2(mal, "txeob %08x" NL, r);
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mal_schedule_poll(mal);
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set_mal_dcrn(mal, MAL_TXEOBISR, r);
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#ifdef CONFIG_PPC_DCR_NATIVE
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if (mal_has_feature(mal, MAL_FTR_CLEAR_ICINTSTAT))
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mtdcri(SDR0, DCRN_SDR_ICINTSTAT,
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(mfdcri(SDR0, DCRN_SDR_ICINTSTAT) | ICINTSTAT_ICTX));
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#endif
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return IRQ_HANDLED;
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}
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static irqreturn_t mal_rxeob(int irq, void *dev_instance)
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{
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struct mal_instance *mal = dev_instance;
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u32 r = get_mal_dcrn(mal, MAL_RXEOBISR);
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MAL_DBG2(mal, "rxeob %08x" NL, r);
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mal_schedule_poll(mal);
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set_mal_dcrn(mal, MAL_RXEOBISR, r);
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#ifdef CONFIG_PPC_DCR_NATIVE
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if (mal_has_feature(mal, MAL_FTR_CLEAR_ICINTSTAT))
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mtdcri(SDR0, DCRN_SDR_ICINTSTAT,
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(mfdcri(SDR0, DCRN_SDR_ICINTSTAT) | ICINTSTAT_ICRX));
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#endif
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return IRQ_HANDLED;
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}
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static irqreturn_t mal_txde(int irq, void *dev_instance)
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{
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struct mal_instance *mal = dev_instance;
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u32 deir = get_mal_dcrn(mal, MAL_TXDEIR);
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set_mal_dcrn(mal, MAL_TXDEIR, deir);
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MAL_DBG(mal, "txde %08x" NL, deir);
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if (net_ratelimit())
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printk(KERN_ERR
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"mal%d: TX descriptor error (TXDEIR = 0x%08x)\n",
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mal->index, deir);
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return IRQ_HANDLED;
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}
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static irqreturn_t mal_rxde(int irq, void *dev_instance)
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{
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struct mal_instance *mal = dev_instance;
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struct list_head *l;
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u32 deir = get_mal_dcrn(mal, MAL_RXDEIR);
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MAL_DBG(mal, "rxde %08x" NL, deir);
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list_for_each(l, &mal->list) {
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struct mal_commac *mc = list_entry(l, struct mal_commac, list);
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if (deir & mc->rx_chan_mask) {
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set_bit(MAL_COMMAC_RX_STOPPED, &mc->flags);
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mc->ops->rxde(mc->dev);
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}
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}
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mal_schedule_poll(mal);
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set_mal_dcrn(mal, MAL_RXDEIR, deir);
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return IRQ_HANDLED;
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}
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static irqreturn_t mal_int(int irq, void *dev_instance)
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{
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struct mal_instance *mal = dev_instance;
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u32 esr = get_mal_dcrn(mal, MAL_ESR);
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if (esr & MAL_ESR_EVB) {
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/* descriptor error */
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if (esr & MAL_ESR_DE) {
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if (esr & MAL_ESR_CIDT)
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return mal_rxde(irq, dev_instance);
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else
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return mal_txde(irq, dev_instance);
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} else { /* SERR */
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return mal_serr(irq, dev_instance);
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}
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}
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return IRQ_HANDLED;
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}
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void mal_poll_disable(struct mal_instance *mal, struct mal_commac *commac)
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{
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/* Spinlock-type semantics: only one caller disable poll at a time */
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while (test_and_set_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags))
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msleep(1);
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/* Synchronize with the MAL NAPI poller */
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napi_synchronize(&mal->napi);
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}
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void mal_poll_enable(struct mal_instance *mal, struct mal_commac *commac)
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{
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smp_wmb();
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clear_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags);
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/* Feels better to trigger a poll here to catch up with events that
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* may have happened on this channel while disabled. It will most
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* probably be delayed until the next interrupt but that's mostly a
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* non-issue in the context where this is called.
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*/
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napi_schedule(&mal->napi);
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}
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static int mal_poll(struct napi_struct *napi, int budget)
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{
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struct mal_instance *mal = container_of(napi, struct mal_instance, napi);
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struct list_head *l;
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int received = 0;
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unsigned long flags;
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MAL_DBG2(mal, "poll(%d)" NL, budget);
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/* Process TX skbs */
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list_for_each(l, &mal->poll_list) {
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struct mal_commac *mc =
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list_entry(l, struct mal_commac, poll_list);
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mc->ops->poll_tx(mc->dev);
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}
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/* Process RX skbs.
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*
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* We _might_ need something more smart here to enforce polling
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* fairness.
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*/
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list_for_each(l, &mal->poll_list) {
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struct mal_commac *mc =
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list_entry(l, struct mal_commac, poll_list);
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int n;
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if (unlikely(test_bit(MAL_COMMAC_POLL_DISABLED, &mc->flags)))
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continue;
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n = mc->ops->poll_rx(mc->dev, budget - received);
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if (n) {
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received += n;
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if (received >= budget)
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return budget;
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}
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}
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if (napi_complete_done(napi, received)) {
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/* We need to disable IRQs to protect from RXDE IRQ here */
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spin_lock_irqsave(&mal->lock, flags);
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mal_enable_eob_irq(mal);
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spin_unlock_irqrestore(&mal->lock, flags);
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}
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/* Check for "rotting" packet(s) */
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list_for_each(l, &mal->poll_list) {
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struct mal_commac *mc =
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list_entry(l, struct mal_commac, poll_list);
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if (unlikely(test_bit(MAL_COMMAC_POLL_DISABLED, &mc->flags)))
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continue;
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if (unlikely(mc->ops->peek_rx(mc->dev) ||
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test_bit(MAL_COMMAC_RX_STOPPED, &mc->flags))) {
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MAL_DBG2(mal, "rotting packet" NL);
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if (!napi_reschedule(napi))
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goto more_work;
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spin_lock_irqsave(&mal->lock, flags);
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mal_disable_eob_irq(mal);
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spin_unlock_irqrestore(&mal->lock, flags);
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}
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mc->ops->poll_tx(mc->dev);
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}
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more_work:
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MAL_DBG2(mal, "poll() %d <- %d" NL, budget, received);
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return received;
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}
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|
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static void mal_reset(struct mal_instance *mal)
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{
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int n = 10;
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MAL_DBG(mal, "reset" NL);
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set_mal_dcrn(mal, MAL_CFG, MAL_CFG_SR);
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/* Wait for reset to complete (1 system clock) */
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while ((get_mal_dcrn(mal, MAL_CFG) & MAL_CFG_SR) && n)
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--n;
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if (unlikely(!n))
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printk(KERN_ERR "mal%d: reset timeout\n", mal->index);
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}
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int mal_get_regs_len(struct mal_instance *mal)
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{
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return sizeof(struct emac_ethtool_regs_subhdr) +
|
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sizeof(struct mal_regs);
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}
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|
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void *mal_dump_regs(struct mal_instance *mal, void *buf)
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{
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struct emac_ethtool_regs_subhdr *hdr = buf;
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struct mal_regs *regs = (struct mal_regs *)(hdr + 1);
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int i;
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hdr->version = mal->version;
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|
hdr->index = mal->index;
|
|
|
|
regs->tx_count = mal->num_tx_chans;
|
|
regs->rx_count = mal->num_rx_chans;
|
|
|
|
regs->cfg = get_mal_dcrn(mal, MAL_CFG);
|
|
regs->esr = get_mal_dcrn(mal, MAL_ESR);
|
|
regs->ier = get_mal_dcrn(mal, MAL_IER);
|
|
regs->tx_casr = get_mal_dcrn(mal, MAL_TXCASR);
|
|
regs->tx_carr = get_mal_dcrn(mal, MAL_TXCARR);
|
|
regs->tx_eobisr = get_mal_dcrn(mal, MAL_TXEOBISR);
|
|
regs->tx_deir = get_mal_dcrn(mal, MAL_TXDEIR);
|
|
regs->rx_casr = get_mal_dcrn(mal, MAL_RXCASR);
|
|
regs->rx_carr = get_mal_dcrn(mal, MAL_RXCARR);
|
|
regs->rx_eobisr = get_mal_dcrn(mal, MAL_RXEOBISR);
|
|
regs->rx_deir = get_mal_dcrn(mal, MAL_RXDEIR);
|
|
|
|
for (i = 0; i < regs->tx_count; ++i)
|
|
regs->tx_ctpr[i] = get_mal_dcrn(mal, MAL_TXCTPR(i));
|
|
|
|
for (i = 0; i < regs->rx_count; ++i) {
|
|
regs->rx_ctpr[i] = get_mal_dcrn(mal, MAL_RXCTPR(i));
|
|
regs->rcbs[i] = get_mal_dcrn(mal, MAL_RCBS(i));
|
|
}
|
|
return regs + 1;
|
|
}
|
|
|
|
static int mal_probe(struct platform_device *ofdev)
|
|
{
|
|
struct mal_instance *mal;
|
|
int err = 0, i, bd_size;
|
|
int index = mal_count++;
|
|
unsigned int dcr_base;
|
|
const u32 *prop;
|
|
u32 cfg;
|
|
unsigned long irqflags;
|
|
irq_handler_t hdlr_serr, hdlr_txde, hdlr_rxde;
|
|
|
|
mal = kzalloc(sizeof(struct mal_instance), GFP_KERNEL);
|
|
if (!mal)
|
|
return -ENOMEM;
|
|
|
|
mal->index = index;
|
|
mal->ofdev = ofdev;
|
|
mal->version = of_device_is_compatible(ofdev->dev.of_node, "ibm,mcmal2") ? 2 : 1;
|
|
|
|
MAL_DBG(mal, "probe" NL);
|
|
|
|
prop = of_get_property(ofdev->dev.of_node, "num-tx-chans", NULL);
|
|
if (prop == NULL) {
|
|
printk(KERN_ERR
|
|
"mal%d: can't find MAL num-tx-chans property!\n",
|
|
index);
|
|
err = -ENODEV;
|
|
goto fail;
|
|
}
|
|
mal->num_tx_chans = prop[0];
|
|
|
|
prop = of_get_property(ofdev->dev.of_node, "num-rx-chans", NULL);
|
|
if (prop == NULL) {
|
|
printk(KERN_ERR
|
|
"mal%d: can't find MAL num-rx-chans property!\n",
|
|
index);
|
|
err = -ENODEV;
|
|
goto fail;
|
|
}
|
|
mal->num_rx_chans = prop[0];
|
|
|
|
dcr_base = dcr_resource_start(ofdev->dev.of_node, 0);
|
|
if (dcr_base == 0) {
|
|
printk(KERN_ERR
|
|
"mal%d: can't find DCR resource!\n", index);
|
|
err = -ENODEV;
|
|
goto fail;
|
|
}
|
|
mal->dcr_host = dcr_map(ofdev->dev.of_node, dcr_base, 0x100);
|
|
if (!DCR_MAP_OK(mal->dcr_host)) {
|
|
printk(KERN_ERR
|
|
"mal%d: failed to map DCRs !\n", index);
|
|
err = -ENODEV;
|
|
goto fail;
|
|
}
|
|
|
|
if (of_device_is_compatible(ofdev->dev.of_node, "ibm,mcmal-405ez")) {
|
|
#if defined(CONFIG_IBM_EMAC_MAL_CLR_ICINTSTAT) && \
|
|
defined(CONFIG_IBM_EMAC_MAL_COMMON_ERR)
|
|
mal->features |= (MAL_FTR_CLEAR_ICINTSTAT |
|
|
MAL_FTR_COMMON_ERR_INT);
|
|
#else
|
|
printk(KERN_ERR "%pOF: Support for 405EZ not enabled!\n",
|
|
ofdev->dev.of_node);
|
|
err = -ENODEV;
|
|
goto fail;
|
|
#endif
|
|
}
|
|
|
|
mal->txeob_irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
|
|
mal->rxeob_irq = irq_of_parse_and_map(ofdev->dev.of_node, 1);
|
|
mal->serr_irq = irq_of_parse_and_map(ofdev->dev.of_node, 2);
|
|
|
|
if (mal_has_feature(mal, MAL_FTR_COMMON_ERR_INT)) {
|
|
mal->txde_irq = mal->rxde_irq = mal->serr_irq;
|
|
} else {
|
|
mal->txde_irq = irq_of_parse_and_map(ofdev->dev.of_node, 3);
|
|
mal->rxde_irq = irq_of_parse_and_map(ofdev->dev.of_node, 4);
|
|
}
|
|
|
|
if (!mal->txeob_irq || !mal->rxeob_irq || !mal->serr_irq ||
|
|
!mal->txde_irq || !mal->rxde_irq) {
|
|
printk(KERN_ERR
|
|
"mal%d: failed to map interrupts !\n", index);
|
|
err = -ENODEV;
|
|
goto fail_unmap;
|
|
}
|
|
|
|
INIT_LIST_HEAD(&mal->poll_list);
|
|
INIT_LIST_HEAD(&mal->list);
|
|
spin_lock_init(&mal->lock);
|
|
|
|
init_dummy_netdev(&mal->dummy_dev);
|
|
|
|
netif_napi_add(&mal->dummy_dev, &mal->napi, mal_poll,
|
|
CONFIG_IBM_EMAC_POLL_WEIGHT);
|
|
|
|
/* Load power-on reset defaults */
|
|
mal_reset(mal);
|
|
|
|
/* Set the MAL configuration register */
|
|
cfg = (mal->version == 2) ? MAL2_CFG_DEFAULT : MAL1_CFG_DEFAULT;
|
|
cfg |= MAL_CFG_PLBB | MAL_CFG_OPBBL | MAL_CFG_LEA;
|
|
|
|
/* Current Axon is not happy with priority being non-0, it can
|
|
* deadlock, fix it up here
|
|
*/
|
|
if (of_device_is_compatible(ofdev->dev.of_node, "ibm,mcmal-axon"))
|
|
cfg &= ~(MAL2_CFG_RPP_10 | MAL2_CFG_WPP_10);
|
|
|
|
/* Apply configuration */
|
|
set_mal_dcrn(mal, MAL_CFG, cfg);
|
|
|
|
/* Allocate space for BD rings */
|
|
BUG_ON(mal->num_tx_chans <= 0 || mal->num_tx_chans > 32);
|
|
BUG_ON(mal->num_rx_chans <= 0 || mal->num_rx_chans > 32);
|
|
|
|
bd_size = sizeof(struct mal_descriptor) *
|
|
(NUM_TX_BUFF * mal->num_tx_chans +
|
|
NUM_RX_BUFF * mal->num_rx_chans);
|
|
mal->bd_virt = dma_zalloc_coherent(&ofdev->dev, bd_size, &mal->bd_dma,
|
|
GFP_KERNEL);
|
|
if (mal->bd_virt == NULL) {
|
|
err = -ENOMEM;
|
|
goto fail_unmap;
|
|
}
|
|
|
|
for (i = 0; i < mal->num_tx_chans; ++i)
|
|
set_mal_dcrn(mal, MAL_TXCTPR(i), mal->bd_dma +
|
|
sizeof(struct mal_descriptor) *
|
|
mal_tx_bd_offset(mal, i));
|
|
|
|
for (i = 0; i < mal->num_rx_chans; ++i)
|
|
set_mal_dcrn(mal, MAL_RXCTPR(i), mal->bd_dma +
|
|
sizeof(struct mal_descriptor) *
|
|
mal_rx_bd_offset(mal, i));
|
|
|
|
if (mal_has_feature(mal, MAL_FTR_COMMON_ERR_INT)) {
|
|
irqflags = IRQF_SHARED;
|
|
hdlr_serr = hdlr_txde = hdlr_rxde = mal_int;
|
|
} else {
|
|
irqflags = 0;
|
|
hdlr_serr = mal_serr;
|
|
hdlr_txde = mal_txde;
|
|
hdlr_rxde = mal_rxde;
|
|
}
|
|
|
|
err = request_irq(mal->serr_irq, hdlr_serr, irqflags, "MAL SERR", mal);
|
|
if (err)
|
|
goto fail2;
|
|
err = request_irq(mal->txde_irq, hdlr_txde, irqflags, "MAL TX DE", mal);
|
|
if (err)
|
|
goto fail3;
|
|
err = request_irq(mal->txeob_irq, mal_txeob, 0, "MAL TX EOB", mal);
|
|
if (err)
|
|
goto fail4;
|
|
err = request_irq(mal->rxde_irq, hdlr_rxde, irqflags, "MAL RX DE", mal);
|
|
if (err)
|
|
goto fail5;
|
|
err = request_irq(mal->rxeob_irq, mal_rxeob, 0, "MAL RX EOB", mal);
|
|
if (err)
|
|
goto fail6;
|
|
|
|
/* Enable all MAL SERR interrupt sources */
|
|
set_mal_dcrn(mal, MAL_IER, MAL_IER_EVENTS);
|
|
|
|
/* Enable EOB interrupt */
|
|
mal_enable_eob_irq(mal);
|
|
|
|
printk(KERN_INFO
|
|
"MAL v%d %pOF, %d TX channels, %d RX channels\n",
|
|
mal->version, ofdev->dev.of_node,
|
|
mal->num_tx_chans, mal->num_rx_chans);
|
|
|
|
/* Advertise this instance to the rest of the world */
|
|
wmb();
|
|
platform_set_drvdata(ofdev, mal);
|
|
|
|
return 0;
|
|
|
|
fail6:
|
|
free_irq(mal->rxde_irq, mal);
|
|
fail5:
|
|
free_irq(mal->txeob_irq, mal);
|
|
fail4:
|
|
free_irq(mal->txde_irq, mal);
|
|
fail3:
|
|
free_irq(mal->serr_irq, mal);
|
|
fail2:
|
|
dma_free_coherent(&ofdev->dev, bd_size, mal->bd_virt, mal->bd_dma);
|
|
fail_unmap:
|
|
dcr_unmap(mal->dcr_host, 0x100);
|
|
fail:
|
|
kfree(mal);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int mal_remove(struct platform_device *ofdev)
|
|
{
|
|
struct mal_instance *mal = platform_get_drvdata(ofdev);
|
|
|
|
MAL_DBG(mal, "remove" NL);
|
|
|
|
/* Synchronize with scheduled polling */
|
|
napi_disable(&mal->napi);
|
|
|
|
if (!list_empty(&mal->list))
|
|
/* This is *very* bad */
|
|
WARN(1, KERN_EMERG
|
|
"mal%d: commac list is not empty on remove!\n",
|
|
mal->index);
|
|
|
|
free_irq(mal->serr_irq, mal);
|
|
free_irq(mal->txde_irq, mal);
|
|
free_irq(mal->txeob_irq, mal);
|
|
free_irq(mal->rxde_irq, mal);
|
|
free_irq(mal->rxeob_irq, mal);
|
|
|
|
mal_reset(mal);
|
|
|
|
dma_free_coherent(&ofdev->dev,
|
|
sizeof(struct mal_descriptor) *
|
|
(NUM_TX_BUFF * mal->num_tx_chans +
|
|
NUM_RX_BUFF * mal->num_rx_chans), mal->bd_virt,
|
|
mal->bd_dma);
|
|
kfree(mal);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id mal_platform_match[] =
|
|
{
|
|
{
|
|
.compatible = "ibm,mcmal",
|
|
},
|
|
{
|
|
.compatible = "ibm,mcmal2",
|
|
},
|
|
/* Backward compat */
|
|
{
|
|
.type = "mcmal-dma",
|
|
.compatible = "ibm,mcmal",
|
|
},
|
|
{
|
|
.type = "mcmal-dma",
|
|
.compatible = "ibm,mcmal2",
|
|
},
|
|
{},
|
|
};
|
|
|
|
static struct platform_driver mal_of_driver = {
|
|
.driver = {
|
|
.name = "mcmal",
|
|
.of_match_table = mal_platform_match,
|
|
},
|
|
.probe = mal_probe,
|
|
.remove = mal_remove,
|
|
};
|
|
|
|
int __init mal_init(void)
|
|
{
|
|
return platform_driver_register(&mal_of_driver);
|
|
}
|
|
|
|
void mal_exit(void)
|
|
{
|
|
platform_driver_unregister(&mal_of_driver);
|
|
}
|