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cd6853d3eb
Update copyright to the new legal entity, Intel-NE, Inc., an Intel company. Update copyright for the new year. Signed-off-by: Chien Tung <chien.tin.tung@intel.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
194 lines
6.8 KiB
C
194 lines
6.8 KiB
C
/*
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* Copyright (c) 2006 - 2009 Intel-NE, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef NES_CONTEXT_H
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#define NES_CONTEXT_H
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struct nes_qp_context {
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__le32 misc;
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__le32 cqs;
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__le32 sq_addr_low;
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__le32 sq_addr_high;
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__le32 rq_addr_low;
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__le32 rq_addr_high;
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__le32 misc2;
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__le16 tcpPorts[2];
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__le32 ip0;
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__le32 ip1;
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__le32 ip2;
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__le32 ip3;
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__le32 mss;
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__le32 arp_index_vlan;
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__le32 tcp_state_flow_label;
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__le32 pd_index_wscale;
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__le32 keepalive;
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u32 ts_recent;
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u32 ts_age;
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__le32 snd_nxt;
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__le32 snd_wnd;
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__le32 rcv_nxt;
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__le32 rcv_wnd;
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__le32 snd_max;
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__le32 snd_una;
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u32 srtt;
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__le32 rttvar;
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__le32 ssthresh;
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__le32 cwnd;
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__le32 snd_wl1;
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__le32 snd_wl2;
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__le32 max_snd_wnd;
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__le32 ts_val_delta;
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u32 retransmit;
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u32 probe_cnt;
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u32 hte_index;
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__le32 q2_addr_low;
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__le32 q2_addr_high;
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__le32 ird_index;
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u32 Rsvd3;
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__le32 ird_ord_sizes;
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u32 mrkr_offset;
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__le32 aeq_token_low;
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__le32 aeq_token_high;
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};
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/* QP Context Misc Field */
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#define NES_QPCONTEXT_MISC_IWARP_VER_MASK 0x00000003
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#define NES_QPCONTEXT_MISC_IWARP_VER_SHIFT 0
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#define NES_QPCONTEXT_MISC_EFB_SIZE_MASK 0x000000C0
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#define NES_QPCONTEXT_MISC_EFB_SIZE_SHIFT 6
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#define NES_QPCONTEXT_MISC_RQ_SIZE_MASK 0x00000300
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#define NES_QPCONTEXT_MISC_RQ_SIZE_SHIFT 8
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#define NES_QPCONTEXT_MISC_SQ_SIZE_MASK 0x00000c00
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#define NES_QPCONTEXT_MISC_SQ_SIZE_SHIFT 10
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#define NES_QPCONTEXT_MISC_PCI_FCN_MASK 0x00007000
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#define NES_QPCONTEXT_MISC_PCI_FCN_SHIFT 12
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#define NES_QPCONTEXT_MISC_DUP_ACKS_MASK 0x00070000
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#define NES_QPCONTEXT_MISC_DUP_ACKS_SHIFT 16
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enum nes_qp_context_misc_bits {
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NES_QPCONTEXT_MISC_RX_WQE_SIZE = 0x00000004,
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NES_QPCONTEXT_MISC_IPV4 = 0x00000008,
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NES_QPCONTEXT_MISC_DO_NOT_FRAG = 0x00000010,
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NES_QPCONTEXT_MISC_INSERT_VLAN = 0x00000020,
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NES_QPCONTEXT_MISC_DROS = 0x00008000,
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NES_QPCONTEXT_MISC_WSCALE = 0x00080000,
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NES_QPCONTEXT_MISC_KEEPALIVE = 0x00100000,
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NES_QPCONTEXT_MISC_TIMESTAMP = 0x00200000,
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NES_QPCONTEXT_MISC_SACK = 0x00400000,
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NES_QPCONTEXT_MISC_RDMA_WRITE_EN = 0x00800000,
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NES_QPCONTEXT_MISC_RDMA_READ_EN = 0x01000000,
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NES_QPCONTEXT_MISC_WBIND_EN = 0x10000000,
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NES_QPCONTEXT_MISC_FAST_REGISTER_EN = 0x20000000,
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NES_QPCONTEXT_MISC_PRIV_EN = 0x40000000,
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NES_QPCONTEXT_MISC_NO_NAGLE = 0x80000000
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};
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enum nes_qp_acc_wq_sizes {
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HCONTEXT_TSA_WQ_SIZE_4 = 0,
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HCONTEXT_TSA_WQ_SIZE_32 = 1,
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HCONTEXT_TSA_WQ_SIZE_128 = 2,
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HCONTEXT_TSA_WQ_SIZE_512 = 3
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};
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/* QP Context Misc2 Fields */
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#define NES_QPCONTEXT_MISC2_TTL_MASK 0x000000ff
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#define NES_QPCONTEXT_MISC2_TTL_SHIFT 0
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#define NES_QPCONTEXT_MISC2_HOP_LIMIT_MASK 0x000000ff
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#define NES_QPCONTEXT_MISC2_HOP_LIMIT_SHIFT 0
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#define NES_QPCONTEXT_MISC2_LIMIT_MASK 0x00000300
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#define NES_QPCONTEXT_MISC2_LIMIT_SHIFT 8
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#define NES_QPCONTEXT_MISC2_NIC_INDEX_MASK 0x0000fc00
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#define NES_QPCONTEXT_MISC2_NIC_INDEX_SHIFT 10
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#define NES_QPCONTEXT_MISC2_SRC_IP_MASK 0x001f0000
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#define NES_QPCONTEXT_MISC2_SRC_IP_SHIFT 16
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#define NES_QPCONTEXT_MISC2_TOS_MASK 0xff000000
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#define NES_QPCONTEXT_MISC2_TOS_SHIFT 24
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#define NES_QPCONTEXT_MISC2_TRAFFIC_CLASS_MASK 0xff000000
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#define NES_QPCONTEXT_MISC2_TRAFFIC_CLASS_SHIFT 24
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/* QP Context Tcp State/Flow Label Fields */
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#define NES_QPCONTEXT_TCPFLOW_FLOW_LABEL_MASK 0x000fffff
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#define NES_QPCONTEXT_TCPFLOW_FLOW_LABEL_SHIFT 0
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#define NES_QPCONTEXT_TCPFLOW_TCP_STATE_MASK 0xf0000000
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#define NES_QPCONTEXT_TCPFLOW_TCP_STATE_SHIFT 28
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enum nes_qp_tcp_state {
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NES_QPCONTEXT_TCPSTATE_CLOSED = 1,
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NES_QPCONTEXT_TCPSTATE_EST = 5,
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NES_QPCONTEXT_TCPSTATE_TIME_WAIT = 11,
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};
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/* QP Context PD Index/wscale Fields */
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#define NES_QPCONTEXT_PDWSCALE_RCV_WSCALE_MASK 0x0000000f
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#define NES_QPCONTEXT_PDWSCALE_RCV_WSCALE_SHIFT 0
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#define NES_QPCONTEXT_PDWSCALE_SND_WSCALE_MASK 0x00000f00
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#define NES_QPCONTEXT_PDWSCALE_SND_WSCALE_SHIFT 8
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#define NES_QPCONTEXT_PDWSCALE_PDINDEX_MASK 0xffff0000
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#define NES_QPCONTEXT_PDWSCALE_PDINDEX_SHIFT 16
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/* QP Context Keepalive Fields */
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#define NES_QPCONTEXT_KEEPALIVE_DELTA_MASK 0x0000ffff
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#define NES_QPCONTEXT_KEEPALIVE_DELTA_SHIFT 0
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#define NES_QPCONTEXT_KEEPALIVE_PROBE_CNT_MASK 0x00ff0000
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#define NES_QPCONTEXT_KEEPALIVE_PROBE_CNT_SHIFT 16
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#define NES_QPCONTEXT_KEEPALIVE_INTV_MASK 0xff000000
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#define NES_QPCONTEXT_KEEPALIVE_INTV_SHIFT 24
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/* QP Context ORD/IRD Fields */
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#define NES_QPCONTEXT_ORDIRD_ORDSIZE_MASK 0x0000007f
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#define NES_QPCONTEXT_ORDIRD_ORDSIZE_SHIFT 0
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#define NES_QPCONTEXT_ORDIRD_IRDSIZE_MASK 0x00030000
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#define NES_QPCONTEXT_ORDIRD_IRDSIZE_SHIFT 16
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#define NES_QPCONTEXT_ORDIRD_IWARP_MODE_MASK 0x30000000
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#define NES_QPCONTEXT_ORDIRD_IWARP_MODE_SHIFT 28
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enum nes_ord_ird_bits {
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NES_QPCONTEXT_ORDIRD_WRPDU = 0x02000000,
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NES_QPCONTEXT_ORDIRD_LSMM_PRESENT = 0x04000000,
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NES_QPCONTEXT_ORDIRD_ALSMM = 0x08000000,
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NES_QPCONTEXT_ORDIRD_AAH = 0x40000000,
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NES_QPCONTEXT_ORDIRD_RNMC = 0x80000000
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};
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enum nes_iwarp_qp_state {
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NES_QPCONTEXT_IWARP_STATE_NONEXIST = 0,
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NES_QPCONTEXT_IWARP_STATE_IDLE = 1,
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NES_QPCONTEXT_IWARP_STATE_RTS = 2,
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NES_QPCONTEXT_IWARP_STATE_CLOSING = 3,
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NES_QPCONTEXT_IWARP_STATE_TERMINATE = 5,
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NES_QPCONTEXT_IWARP_STATE_ERROR = 6
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};
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#endif /* NES_CONTEXT_H */
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