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b97872d4eb
The OPP properties, like "operating-points", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can create an OPP table. Add such missing properties. Fix other missing properties (like clocks, supply, clock latency) as well to make it all work. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
392 lines
8.6 KiB
Plaintext
392 lines
8.6 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright 2013 Freescale Semiconductor, Inc.
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "imx6dl-pinfunc.h"
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#include "imx6qdl.dtsi"
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/ {
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aliases {
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i2c3 = &i2c4;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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operating-points = <
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/* kHz uV */
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996000 1250000
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792000 1175000
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396000 1150000
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>;
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fsl,soc-operating-points = <
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/* ARM kHz SOC-PU uV */
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996000 1175000
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792000 1175000
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396000 1175000
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>;
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clock-latency = <61036>; /* two CLK32 periods */
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#cooling-cells = <2>;
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clocks = <&clks IMX6QDL_CLK_ARM>,
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<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
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<&clks IMX6QDL_CLK_STEP>,
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<&clks IMX6QDL_CLK_PLL1_SW>,
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<&clks IMX6QDL_CLK_PLL1_SYS>;
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clock-names = "arm", "pll2_pfd2_396m", "step",
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"pll1_sw", "pll1_sys";
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arm-supply = <®_arm>;
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pu-supply = <®_pu>;
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soc-supply = <®_soc>;
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};
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cpu@1 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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operating-points = <
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/* kHz uV */
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996000 1250000
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792000 1175000
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396000 1150000
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>;
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fsl,soc-operating-points = <
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/* ARM kHz SOC-PU uV */
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996000 1175000
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792000 1175000
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396000 1175000
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>;
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clks IMX6QDL_CLK_ARM>,
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<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
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<&clks IMX6QDL_CLK_STEP>,
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<&clks IMX6QDL_CLK_PLL1_SW>,
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<&clks IMX6QDL_CLK_PLL1_SYS>;
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clock-names = "arm", "pll2_pfd2_396m", "step",
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"pll1_sw", "pll1_sys";
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arm-supply = <®_arm>;
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pu-supply = <®_pu>;
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soc-supply = <®_soc>;
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};
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};
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soc {
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ocram: sram@900000 {
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compatible = "mmio-sram";
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reg = <0x00900000 0x20000>;
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clocks = <&clks IMX6QDL_CLK_OCRAM>;
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};
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aips1: aips-bus@2000000 {
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iomuxc: iomuxc@20e0000 {
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compatible = "fsl,imx6dl-iomuxc";
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};
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pxp: pxp@20f0000 {
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reg = <0x020f0000 0x4000>;
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interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
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};
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epdc: epdc@20f4000 {
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reg = <0x020f4000 0x4000>;
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interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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aips2: aips-bus@2100000 {
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i2c4: i2c@21f8000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
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reg = <0x021f8000 0x4000>;
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interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6DL_CLK_I2C4>;
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status = "disabled";
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};
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};
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};
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capture-subsystem {
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compatible = "fsl,imx-capture-subsystem";
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ports = <&ipu1_csi0>, <&ipu1_csi1>;
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};
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display-subsystem {
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compatible = "fsl,imx-display-subsystem";
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ports = <&ipu1_di0>, <&ipu1_di1>;
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};
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};
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&gpio1 {
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gpio-ranges = <&iomuxc 0 131 2>, <&iomuxc 2 137 8>, <&iomuxc 10 189 2>,
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<&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>,
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<&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>,
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<&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>,
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<&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>,
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<&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>,
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<&iomuxc 30 129 1>, <&iomuxc 31 122 1>;
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};
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&gpio2 {
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gpio-ranges = <&iomuxc 0 161 8>, <&iomuxc 8 208 8>, <&iomuxc 16 74 1>,
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<&iomuxc 17 73 1>, <&iomuxc 18 72 1>, <&iomuxc 19 71 1>,
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<&iomuxc 20 70 1>, <&iomuxc 21 69 1>, <&iomuxc 22 68 1>,
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<&iomuxc 23 79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>,
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<&iomuxc 28 113 4>;
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};
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&gpio3 {
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gpio-ranges = <&iomuxc 0 97 2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>,
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<&iomuxc 16 81 16>;
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};
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&gpio4 {
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gpio-ranges = <&iomuxc 5 136 1>, <&iomuxc 6 145 1>, <&iomuxc 7 150 1>,
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<&iomuxc 8 146 1>, <&iomuxc 9 151 1>, <&iomuxc 10 147 1>,
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<&iomuxc 11 152 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>,
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<&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16 39 7>,
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<&iomuxc 23 56 1>, <&iomuxc 24 61 7>, <&iomuxc 31 46 1>;
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};
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&gpio5 {
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gpio-ranges = <&iomuxc 0 120 1>, <&iomuxc 2 77 1>, <&iomuxc 4 76 1>,
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<&iomuxc 5 47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>,
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<&iomuxc 19 36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>,
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<&iomuxc 22 29 6>, <&iomuxc 28 19 4>;
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};
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&gpio6 {
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gpio-ranges = <&iomuxc 0 23 6>, <&iomuxc 6 75 1>, <&iomuxc 7 156 1>,
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<&iomuxc 8 155 1>, <&iomuxc 9 170 1>, <&iomuxc 10 169 1>,
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<&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>,
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<&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>,
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<&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>,
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<&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31 78 1>;
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};
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&gpio7 {
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gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc 1 201 1>, <&iomuxc 2 196 1>,
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<&iomuxc 3 195 1>, <&iomuxc 4 197 4>, <&iomuxc 8 205 1>,
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<&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>;
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};
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&gpr {
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ipu1_csi0_mux {
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compatible = "video-mux";
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mux-controls = <&mux 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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ipu1_csi0_mux_from_mipi_vc0: endpoint {
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remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
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};
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};
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port@1 {
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reg = <1>;
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ipu1_csi0_mux_from_mipi_vc1: endpoint {
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remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;
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};
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};
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port@2 {
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reg = <2>;
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ipu1_csi0_mux_from_mipi_vc2: endpoint {
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remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;
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};
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};
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port@3 {
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reg = <3>;
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ipu1_csi0_mux_from_mipi_vc3: endpoint {
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remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;
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};
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};
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port@4 {
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reg = <4>;
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ipu1_csi0_mux_from_parallel_sensor: endpoint {
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};
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};
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port@5 {
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reg = <5>;
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ipu1_csi0_mux_to_ipu1_csi0: endpoint {
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remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
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};
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};
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};
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ipu1_csi1_mux {
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compatible = "video-mux";
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mux-controls = <&mux 1>;
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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ipu1_csi1_mux_from_mipi_vc0: endpoint {
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remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;
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};
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};
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port@1 {
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reg = <1>;
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ipu1_csi1_mux_from_mipi_vc1: endpoint {
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remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;
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};
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};
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port@2 {
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reg = <2>;
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ipu1_csi1_mux_from_mipi_vc2: endpoint {
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remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;
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};
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};
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port@3 {
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reg = <3>;
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ipu1_csi1_mux_from_mipi_vc3: endpoint {
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remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;
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};
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};
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port@4 {
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reg = <4>;
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ipu1_csi1_mux_from_parallel_sensor: endpoint {
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};
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};
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port@5 {
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reg = <5>;
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ipu1_csi1_mux_to_ipu1_csi1: endpoint {
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remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;
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};
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};
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};
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};
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&gpt {
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compatible = "fsl,imx6dl-gpt";
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};
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&hdmi {
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compatible = "fsl,imx6dl-hdmi";
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};
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&ipu1_csi1 {
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ipu1_csi1_from_ipu1_csi1_mux: endpoint {
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remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
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};
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};
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&ldb {
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clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
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<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
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<&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
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clock-names = "di0_pll", "di1_pll",
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"di0_sel", "di1_sel",
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"di0", "di1";
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};
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&mipi_csi {
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_vc0_to_ipu1_csi0_mux: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
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};
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mipi_vc0_to_ipu1_csi1_mux: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
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};
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};
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port@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_vc1_to_ipu1_csi0_mux: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;
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};
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mipi_vc1_to_ipu1_csi1_mux: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;
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};
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};
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port@3 {
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reg = <3>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_vc2_to_ipu1_csi0_mux: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;
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};
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mipi_vc2_to_ipu1_csi1_mux: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;
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};
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};
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port@4 {
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reg = <4>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_vc3_to_ipu1_csi0_mux: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;
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};
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mipi_vc3_to_ipu1_csi1_mux: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;
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};
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};
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};
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&mux {
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mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
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<0x34 0x00000038>, /* IPU_CSI1_MUX */
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<0x0c 0x0000000c>, /* HDMI_MUX_CTL */
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<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
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<0x0c 0x00000300>, /* LVDS1_MUX_CTL */
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<0x28 0x00000003>, /* DCIC1_MUX_CTL */
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<0x28 0x0000000c>; /* DCIC2_MUX_CTL */
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};
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&vpu {
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compatible = "fsl,imx6dl-vpu", "cnm,coda960";
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};
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