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d7bb1ac89b
Add the ASIC-specific code for Gaudi2. Supply (almost) all of the function callbacks that the driver's common code need to initialize, finalize and submit workloads to the Gaudi2 ASIC. It also contains the code to initialize the F/W of the Gaudi2 ASIC and to receive events from the F/W. It contains new debugfs entry to dump razwi events. razwi is a case where the device's engines create a transaction that reaches an invalid destination. Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
134 lines
3.3 KiB
C
134 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2022 HabanaLabs, Ltd.
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* All Rights Reserved.
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*/
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#include "habanalabs.h"
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#define VCMD_CONTROL_OFFSET 0x40 /* SWREG16 */
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#define VCMD_IRQ_STATUS_OFFSET 0x44 /* SWREG17 */
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#define VCMD_IRQ_STATUS_ENDCMD_MASK 0x1
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#define VCMD_IRQ_STATUS_BUSERR_MASK 0x2
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#define VCMD_IRQ_STATUS_TIMEOUT_MASK 0x4
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#define VCMD_IRQ_STATUS_CMDERR_MASK 0x8
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#define VCMD_IRQ_STATUS_ABORT_MASK 0x10
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#define VCMD_IRQ_STATUS_RESET_MASK 0x20
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static void dec_print_abnrm_intr_source(struct hl_device *hdev, u32 irq_status)
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{
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const char *format = "abnormal interrupt source:%s%s%s%s%s%s\n";
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char *intr_source[6] = {"Unknown", "", "", "", "", ""};
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int i = 0;
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if (!irq_status)
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return;
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if (irq_status & VCMD_IRQ_STATUS_ENDCMD_MASK)
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intr_source[i++] = " ENDCMD";
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if (irq_status & VCMD_IRQ_STATUS_BUSERR_MASK)
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intr_source[i++] = " BUSERR";
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if (irq_status & VCMD_IRQ_STATUS_TIMEOUT_MASK)
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intr_source[i++] = " TIMEOUT";
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if (irq_status & VCMD_IRQ_STATUS_CMDERR_MASK)
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intr_source[i++] = " CMDERR";
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if (irq_status & VCMD_IRQ_STATUS_ABORT_MASK)
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intr_source[i++] = " ABORT";
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if (irq_status & VCMD_IRQ_STATUS_RESET_MASK)
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intr_source[i++] = " RESET";
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dev_err(hdev->dev, format, intr_source[0], intr_source[1],
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intr_source[2], intr_source[3], intr_source[4], intr_source[5]);
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}
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static void dec_error_intr_work(struct hl_device *hdev, u32 base_addr, u32 core_id)
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{
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bool reset_required = false;
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u32 irq_status;
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irq_status = RREG32(base_addr + VCMD_IRQ_STATUS_OFFSET);
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dev_err(hdev->dev, "Decoder abnormal interrupt %#x, core %d\n", irq_status, core_id);
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dec_print_abnrm_intr_source(hdev, irq_status);
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if (irq_status & VCMD_IRQ_STATUS_TIMEOUT_MASK)
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reset_required = true;
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/* Clear the interrupt */
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WREG32(base_addr + VCMD_IRQ_STATUS_OFFSET, irq_status);
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/* Flush the interrupt clear */
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RREG32(base_addr + VCMD_IRQ_STATUS_OFFSET);
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if (reset_required)
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hl_device_reset(hdev, HL_DRV_RESET_HARD);
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}
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static void dec_completion_abnrm(struct work_struct *work)
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{
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struct hl_dec *dec = container_of(work, struct hl_dec, completion_abnrm_work);
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struct hl_device *hdev = dec->hdev;
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dec_error_intr_work(hdev, dec->base_addr, dec->core_id);
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}
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void hl_dec_fini(struct hl_device *hdev)
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{
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kfree(hdev->dec);
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}
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int hl_dec_init(struct hl_device *hdev)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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struct hl_dec *dec;
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int rc, j;
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/* if max core is 0, nothing to do*/
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if (!prop->max_dec)
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return 0;
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hdev->dec = kcalloc(prop->max_dec, sizeof(struct hl_dec), GFP_KERNEL);
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if (!hdev->dec)
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return -ENOMEM;
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for (j = 0 ; j < prop->max_dec ; j++) {
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dec = hdev->dec + j;
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dec->hdev = hdev;
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INIT_WORK(&dec->completion_abnrm_work, dec_completion_abnrm);
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dec->core_id = j;
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dec->base_addr = hdev->asic_funcs->get_dec_base_addr(hdev, j);
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if (!dec->base_addr) {
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dev_err(hdev->dev, "Invalid base address of decoder %d\n", j);
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rc = -EINVAL;
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goto err_dec_fini;
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}
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}
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return 0;
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err_dec_fini:
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hl_dec_fini(hdev);
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return rc;
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}
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void hl_dec_ctx_fini(struct hl_ctx *ctx)
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{
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struct hl_device *hdev = ctx->hdev;
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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struct hl_dec *dec;
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int j;
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for (j = 0 ; j < prop->max_dec ; j++) {
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if (!!(prop->decoder_enabled_mask & BIT(j))) {
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dec = hdev->dec + j;
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/* Stop the decoder */
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WREG32(dec->base_addr + VCMD_CONTROL_OFFSET, 0);
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}
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}
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}
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