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There are a few MSRs and control register bits that the kernel normally needs to modify during boot. But, TDX disallows modification of these registers to help provide consistent security guarantees. Fortunately, TDX ensures that these are all in the correct state before the kernel loads, which means the kernel does not need to modify them. The conditions to avoid are: * Any writes to the EFER MSR * Clearing CR4.MCE This theoretically makes the guest boot more fragile. If, for instance, EFER was set up incorrectly and a WRMSR was performed, it will trigger early exception panic or a triple fault, if it's before early exceptions are set up. However, this is likely to trip up the guest BIOS long before control reaches the kernel. In any case, these kinds of problems are unlikely to occur in production environments, and developers have good debug tools to fix them quickly. Change the common boot code to work on TDX and non-TDX systems. This should have no functional effect on non-TDX systems. Signed-off-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Reviewed-by: Andi Kleen <ak@linux.intel.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lkml.kernel.org/r/20220405232939.73860-24-kirill.shutemov@linux.intel.com
21 lines
495 B
C
21 lines
495 B
C
#ifndef BOOT_COMPRESSED_PAGETABLE_H
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#define BOOT_COMPRESSED_PAGETABLE_H
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#define TRAMPOLINE_32BIT_SIZE (2 * PAGE_SIZE)
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#define TRAMPOLINE_32BIT_PGTABLE_OFFSET 0
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#define TRAMPOLINE_32BIT_CODE_OFFSET PAGE_SIZE
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#define TRAMPOLINE_32BIT_CODE_SIZE 0x80
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#define TRAMPOLINE_32BIT_STACK_END TRAMPOLINE_32BIT_SIZE
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#ifndef __ASSEMBLER__
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extern unsigned long *trampoline_32bit;
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extern void trampoline_32bit_src(void *return_ptr);
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#endif /* __ASSEMBLER__ */
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#endif /* BOOT_COMPRESSED_PAGETABLE_H */
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