Anup Patel 6b7ce8927b irqchip: RISC-V per-HART local interrupt controller driver ... The RISC-V per-HART local interrupt controller manages software interrupts, timer interrupts, external interrupts (which are routed via the platform level interrupt controller) and other per-HART local interrupts. We add a driver for the RISC-V local interrupt controller, which eventually replaces the RISC-V architecture code, allowing for a better split between arch code and drivers. The driver is compliant with RISC-V Hart-Level Interrupt Controller DT bindings located at: Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt Co-developed-by: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> [Palmer: Cleaned up warnings] Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>		2020-06-09 19:11:21 -07:00
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asm	irqchip: RISC-V per-HART local interrupt controller driver	2020-06-09 19:11:21 -07:00
uapi/asm	riscv, bpf: Add missing uapi header for BPF_PROG_TYPE_PERF_EVENT programs	2019-12-19 16:03:31 +01:00