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69f1d1a6ac
* 'next/devel' of ssh://master.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: (128 commits) ARM: S5P64X0: External Interrupt Support ARM: EXYNOS4: Enable MFC on Samsung NURI ARM: EXYNOS4: Enable MFC on universal_c210 ARM: S5PV210: Enable MFC on Goni ARM: S5P: Add support for MFC device ARM: EXYNOS4: Add support FIMD on SMDKC210 ARM: EXYNOS4: Add platform device and helper functions for FIMD ARM: EXYNOS4: Add resource definition for FIMD ARM: EXYNOS4: Change devname for FIMD clkdev ARM: SAMSUNG: Add IRQ_I2S0 definition ARM: SAMSUNG: Add platform device for idma ARM: EXYNOS4: Add more registers to be saved and restored for PM ARM: EXYNOS4: Add more register addresses of CMU ARM: EXYNOS4: Add platform device for dwmci driver ARM: EXYNOS4: configure rtc-s3c on NURI ARM: EXYNOS4: configure MAX8903 secondary charger on NURI ARM: EXYNOS4: configure ADC on NURI ARM: EXYNOS4: configure MAX17042 fuel gauge on NURI ARM: EXYNOS4: configure regulators and PMIC(MAX8997) on NURI ARM: EXYNOS4: Increase NR_IRQS for devices with more IRQs ... Fix up tons of silly conflicts: - arch/arm/mach-davinci/include/mach/psc.h - arch/arm/mach-exynos4/Kconfig - arch/arm/mach-exynos4/mach-smdkc210.c - arch/arm/mach-exynos4/pm.c - arch/arm/mach-imx/mm-imx1.c - arch/arm/mach-imx/mm-imx21.c - arch/arm/mach-imx/mm-imx25.c - arch/arm/mach-imx/mm-imx27.c - arch/arm/mach-imx/mm-imx31.c - arch/arm/mach-imx/mm-imx35.c - arch/arm/mach-mx5/mm.c - arch/arm/mach-s5pv210/mach-goni.c - arch/arm/mm/Kconfig
365 lines
8.4 KiB
C
365 lines
8.4 KiB
C
/* linux/arch/arm/plat-s3c/pm.c
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2004-2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C common power management (suspend to ram) support.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/suspend.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/serial_core.h>
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include <asm/suspend.h>
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#include <mach/hardware.h>
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#include <mach/map.h>
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#include <plat/regs-serial.h>
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#include <mach/regs-clock.h>
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#include <mach/regs-irq.h>
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#include <asm/irq.h>
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#include <plat/pm.h>
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#include <mach/pm-core.h>
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/* for external use */
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unsigned long s3c_pm_flags;
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/* Debug code:
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*
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* This code supports debug output to the low level UARTs for use on
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* resume before the console layer is available.
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*/
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#ifdef CONFIG_SAMSUNG_PM_DEBUG
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extern void printascii(const char *);
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void s3c_pm_dbg(const char *fmt, ...)
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{
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va_list va;
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char buff[256];
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va_start(va, fmt);
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vsprintf(buff, fmt, va);
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va_end(va);
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printascii(buff);
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}
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static inline void s3c_pm_debug_init(void)
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{
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/* restart uart clocks so we can use them to output */
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s3c_pm_debug_init_uart();
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}
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#else
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#define s3c_pm_debug_init() do { } while(0)
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#endif /* CONFIG_SAMSUNG_PM_DEBUG */
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/* Save the UART configurations if we are configured for debug. */
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unsigned char pm_uart_udivslot;
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#ifdef CONFIG_SAMSUNG_PM_DEBUG
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struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS];
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static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save)
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{
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void __iomem *regs = S3C_VA_UARTx(uart);
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save->ulcon = __raw_readl(regs + S3C2410_ULCON);
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save->ucon = __raw_readl(regs + S3C2410_UCON);
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save->ufcon = __raw_readl(regs + S3C2410_UFCON);
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save->umcon = __raw_readl(regs + S3C2410_UMCON);
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save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);
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if (pm_uart_udivslot)
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save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT);
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S3C_PMDBG("UART[%d]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n",
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uart, save->ulcon, save->ucon, save->ufcon, save->ubrdiv);
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}
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static void s3c_pm_save_uarts(void)
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{
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struct pm_uart_save *save = uart_save;
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unsigned int uart;
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for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++)
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s3c_pm_save_uart(uart, save);
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}
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static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save)
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{
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void __iomem *regs = S3C_VA_UARTx(uart);
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s3c_pm_arch_update_uart(regs, save);
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__raw_writel(save->ulcon, regs + S3C2410_ULCON);
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__raw_writel(save->ucon, regs + S3C2410_UCON);
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__raw_writel(save->ufcon, regs + S3C2410_UFCON);
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__raw_writel(save->umcon, regs + S3C2410_UMCON);
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__raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV);
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if (pm_uart_udivslot)
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__raw_writel(save->udivslot, regs + S3C2443_DIVSLOT);
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}
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static void s3c_pm_restore_uarts(void)
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{
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struct pm_uart_save *save = uart_save;
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unsigned int uart;
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for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++)
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s3c_pm_restore_uart(uart, save);
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}
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#else
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static void s3c_pm_save_uarts(void) { }
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static void s3c_pm_restore_uarts(void) { }
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#endif
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/* The IRQ ext-int code goes here, it is too small to currently bother
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* with its own file. */
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unsigned long s3c_irqwake_intmask = 0xffffffffL;
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unsigned long s3c_irqwake_eintmask = 0xffffffffL;
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int s3c_irqext_wake(struct irq_data *data, unsigned int state)
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{
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unsigned long bit = 1L << IRQ_EINT_BIT(data->irq);
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if (!(s3c_irqwake_eintallow & bit))
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return -ENOENT;
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printk(KERN_INFO "wake %s for irq %d\n",
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state ? "enabled" : "disabled", data->irq);
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if (!state)
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s3c_irqwake_eintmask |= bit;
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else
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s3c_irqwake_eintmask &= ~bit;
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return 0;
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}
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/* helper functions to save and restore register state */
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/**
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* s3c_pm_do_save() - save a set of registers for restoration on resume.
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* @ptr: Pointer to an array of registers.
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* @count: Size of the ptr array.
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*
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* Run through the list of registers given, saving their contents in the
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* array for later restoration when we wakeup.
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*/
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void s3c_pm_do_save(struct sleep_save *ptr, int count)
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{
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for (; count > 0; count--, ptr++) {
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ptr->val = __raw_readl(ptr->reg);
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S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val);
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}
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}
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/**
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* s3c_pm_do_restore() - restore register values from the save list.
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* @ptr: Pointer to an array of registers.
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* @count: Size of the ptr array.
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*
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* Restore the register values saved from s3c_pm_do_save().
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*
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* Note, we do not use S3C_PMDBG() in here, as the system may not have
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* restore the UARTs state yet
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*/
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void s3c_pm_do_restore(struct sleep_save *ptr, int count)
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{
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for (; count > 0; count--, ptr++) {
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printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
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ptr->reg, ptr->val, __raw_readl(ptr->reg));
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__raw_writel(ptr->val, ptr->reg);
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}
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}
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/**
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* s3c_pm_do_restore_core() - early restore register values from save list.
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*
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* This is similar to s3c_pm_do_restore() except we try and minimise the
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* side effects of the function in case registers that hardware might need
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* to work has been restored.
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*
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* WARNING: Do not put any debug in here that may effect memory or use
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* peripherals, as things may be changing!
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*/
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void s3c_pm_do_restore_core(struct sleep_save *ptr, int count)
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{
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for (; count > 0; count--, ptr++)
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__raw_writel(ptr->val, ptr->reg);
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}
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/* s3c2410_pm_show_resume_irqs
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*
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* print any IRQs asserted at resume time (ie, we woke from)
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*/
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static void __maybe_unused s3c_pm_show_resume_irqs(int start,
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unsigned long which,
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unsigned long mask)
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{
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int i;
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which &= ~mask;
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for (i = 0; i <= 31; i++) {
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if (which & (1L<<i)) {
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S3C_PMDBG("IRQ %d asserted at resume\n", start+i);
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}
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}
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}
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void (*pm_cpu_prep)(void);
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int (*pm_cpu_sleep)(unsigned long);
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#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
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/* s3c_pm_enter
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*
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* central control for sleep/resume process
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*/
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static int s3c_pm_enter(suspend_state_t state)
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{
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/* ensure the debug is initialised (if enabled) */
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s3c_pm_debug_init();
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S3C_PMDBG("%s(%d)\n", __func__, state);
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if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
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printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__);
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return -EINVAL;
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}
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/* check if we have anything to wake-up with... bad things seem
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* to happen if you suspend with no wakeup (system will often
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* require a full power-cycle)
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*/
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if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
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!any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
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printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
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printk(KERN_ERR "%s: Aborting sleep\n", __func__);
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return -EINVAL;
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}
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/* save all necessary core registers not covered by the drivers */
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s3c_pm_save_gpios();
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s3c_pm_saved_gpios();
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s3c_pm_save_uarts();
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s3c_pm_save_core();
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/* set the irq configuration for wake */
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s3c_pm_configure_extint();
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S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
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s3c_irqwake_intmask, s3c_irqwake_eintmask);
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s3c_pm_arch_prepare_irqs();
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/* call cpu specific preparation */
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pm_cpu_prep();
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/* flush cache back to ram */
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flush_cache_all();
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s3c_pm_check_store();
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/* send the cpu to sleep... */
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s3c_pm_arch_stop_clocks();
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/* this will also act as our return point from when
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* we resume as it saves its own register state and restores it
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* during the resume. */
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cpu_suspend(0, pm_cpu_sleep);
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/* restore the system state */
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s3c_pm_restore_core();
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s3c_pm_restore_uarts();
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s3c_pm_restore_gpios();
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s3c_pm_restored_gpios();
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s3c_pm_debug_init();
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/* check what irq (if any) restored the system */
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s3c_pm_arch_show_resume_irqs();
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S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);
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/* LEDs should now be 1110 */
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s3c_pm_debug_smdkled(1 << 1, 0);
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s3c_pm_check_restore();
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/* ok, let's return from sleep */
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S3C_PMDBG("S3C PM Resume (post-restore)\n");
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return 0;
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}
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static int s3c_pm_prepare(void)
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{
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/* prepare check area if configured */
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s3c_pm_check_prepare();
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return 0;
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}
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static void s3c_pm_finish(void)
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{
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s3c_pm_check_cleanup();
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}
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static const struct platform_suspend_ops s3c_pm_ops = {
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.enter = s3c_pm_enter,
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.prepare = s3c_pm_prepare,
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.finish = s3c_pm_finish,
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.valid = suspend_valid_only_mem,
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};
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/* s3c_pm_init
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*
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* Attach the power management functions. This should be called
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* from the board specific initialisation if the board supports
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* it.
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*/
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int __init s3c_pm_init(void)
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{
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printk("S3C Power Management, Copyright 2004 Simtec Electronics\n");
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suspend_set_ops(&s3c_pm_ops);
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return 0;
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}
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