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Following patch V8 adds support for Cavium Liquidio pci express based 10Gig ethernet adapters. 1) Consolidated all debug macros to either call dev_* or netdev_* macros directly, feedback from previous patch. 2) Changed soft commands to avoid crash when running in interrupt context. 3) Fixed link status not reflecting correct status when NetworkManager is running. Added MODULE_FIRMWARE declarations. Following were the previous patches. Patch V7: 1) Minor comments from v6 release regarding debug statements. 2) Fix for large multicast lists. 3) Fixed lockup issue if port initialization fails. 4) Enabled MSI by default. https://patchwork.ozlabs.org/patch/464441/ Patch V6: 1) Addressed the uint64 vs u64 issue, feedback from previous patch. 2) Consolidated some receive processing routines. 3) Removed link status polling method. https://patchwork.ozlabs.org/patch/459514/ Patch V5: Based on the feedback from earlier patches with regards to consolidation of common functions like device init, register programming for cn66xx and cn68xx devices. https://patchwork.ozlabs.org/patch/438979/ Patch V4: Following were the changes based on the feedback from earlier patch: 1) Added mmiowb while synchronizing queue updates and other hw interactions. 2) Statistics will now be incremented non-atomically per each ring. liquidio_get_stats will add stats of each ring while reporting the total statistics counts. 3) Modified liquidio_ioctl to return proper return codes. 4) Modified device naming to use standard Ethernet naming. 5) Global function names in the driver will have lio_/liquidio_/octeon_ prefix. 6) Ethtool related changes for: Removed redundant stats and jiffies. Use default ethtool handler of link status. Speed setting will make use of ethtool_cmd_speed_set. 7) Added checks for pci_map_* return codes. 8) Check for signals while waiting in interruptible mode https://patchwork.ozlabs.org/patch/435073/ Patch v3: Implemented feedback from previous patch like: Removed NAPI Config and DEBUG config options, added BQL and xmit_more support. https://patchwork.ozlabs.org/patch/422749/ Patch V2: Implemented feedback from previous patch. https://patchwork.ozlabs.org/patch/413539/ First Patch: https://patchwork.ozlabs.org/patch/412946/ Signed-off-by: Derek Chickles <derek.chickles@caviumnetworks.com> Signed-off-by: Satanand Burla <satananda.burla@caviumnetworks.com> Signed-off-by: Felix Manlunas <felix.manlunas@caviumnetworks.com> Signed-off-by: Robert Richter <Robert.Richter@caviumnetworks.com> Signed-off-by: Aleksey Makarov <Aleksey.Makarov@caviumnetworks.com> Signed-off-by: Raghu Vatsavayi <raghu.vatsavayi@caviumnetworks.com> Signed-off-by: David S. Miller <davem@davemloft.net>
724 lines
20 KiB
C
724 lines
20 KiB
C
/**********************************************************************
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* Author: Cavium, Inc.
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*
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* Contact: support@cavium.com
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* Please include "LiquidIO" in the subject.
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*
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* Copyright (c) 2003-2015 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium, Inc. for more information
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**********************************************************************/
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/**
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* @file octeon_console.c
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*/
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#include <linux/version.h>
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#include <linux/types.h>
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#include <linux/list.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/kthread.h>
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#include <linux/netdevice.h>
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#include "octeon_config.h"
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#include "liquidio_common.h"
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#include "octeon_droq.h"
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#include "octeon_iq.h"
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#include "response_manager.h"
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#include "octeon_device.h"
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#include "octeon_nic.h"
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#include "octeon_main.h"
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#include "octeon_network.h"
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#include "cn66xx_regs.h"
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#include "cn66xx_device.h"
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#include "cn68xx_regs.h"
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#include "cn68xx_device.h"
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#include "liquidio_image.h"
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#include "octeon_mem_ops.h"
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static void octeon_remote_lock(void);
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static void octeon_remote_unlock(void);
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static u64 cvmx_bootmem_phy_named_block_find(struct octeon_device *oct,
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const char *name,
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u32 flags);
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#define MIN(a, b) min((a), (b))
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#define CAST_ULL(v) ((u64)(v))
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#define BOOTLOADER_PCI_READ_BUFFER_DATA_ADDR 0x0006c008
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#define BOOTLOADER_PCI_READ_BUFFER_LEN_ADDR 0x0006c004
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#define BOOTLOADER_PCI_READ_BUFFER_OWNER_ADDR 0x0006c000
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#define BOOTLOADER_PCI_READ_DESC_ADDR 0x0006c100
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#define BOOTLOADER_PCI_WRITE_BUFFER_STR_LEN 248
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#define OCTEON_PCI_IO_BUF_OWNER_OCTEON 0x00000001
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#define OCTEON_PCI_IO_BUF_OWNER_HOST 0x00000002
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/** Can change without breaking ABI */
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#define CVMX_BOOTMEM_NUM_NAMED_BLOCKS 64
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/** minimum alignment of bootmem alloced blocks */
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#define CVMX_BOOTMEM_ALIGNMENT_SIZE (16ull)
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/** CVMX bootmem descriptor major version */
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#define CVMX_BOOTMEM_DESC_MAJ_VER 3
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/* CVMX bootmem descriptor minor version */
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#define CVMX_BOOTMEM_DESC_MIN_VER 0
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/* Current versions */
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#define OCTEON_PCI_CONSOLE_MAJOR_VERSION 1
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#define OCTEON_PCI_CONSOLE_MINOR_VERSION 0
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#define OCTEON_PCI_CONSOLE_BLOCK_NAME "__pci_console"
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#define OCTEON_CONSOLE_POLL_INTERVAL_MS 100 /* 10 times per second */
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/* First three members of cvmx_bootmem_desc are left in original
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** positions for backwards compatibility.
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** Assumes big endian target
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*/
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struct cvmx_bootmem_desc {
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/** spinlock to control access to list */
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u32 lock;
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/** flags for indicating various conditions */
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u32 flags;
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u64 head_addr;
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/** incremented changed when incompatible changes made */
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u32 major_version;
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/** incremented changed when compatible changes made,
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* reset to zero when major incremented
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*/
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u32 minor_version;
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u64 app_data_addr;
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u64 app_data_size;
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/** number of elements in named blocks array */
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u32 nb_num_blocks;
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/** length of name array in bootmem blocks */
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u32 named_block_name_len;
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/** address of named memory block descriptors */
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u64 named_block_array_addr;
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};
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/* Structure that defines a single console.
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*
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* Note: when read_index == write_index, the buffer is empty.
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* The actual usable size of each console is console_buf_size -1;
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*/
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struct octeon_pci_console {
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u64 input_base_addr;
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u32 input_read_index;
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u32 input_write_index;
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u64 output_base_addr;
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u32 output_read_index;
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u32 output_write_index;
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u32 lock;
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u32 buf_size;
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};
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/* This is the main container structure that contains all the information
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* about all PCI consoles. The address of this structure is passed to various
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* routines that operation on PCI consoles.
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*/
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struct octeon_pci_console_desc {
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u32 major_version;
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u32 minor_version;
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u32 lock;
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u32 flags;
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u32 num_consoles;
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u32 pad;
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/* must be 64 bit aligned here... */
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/* Array of addresses of octeon_pci_console structures */
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u64 console_addr_array[0];
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/* Implicit storage for console_addr_array */
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};
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/**
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* This macro returns the size of a member of a structure.
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* Logically it is the same as "sizeof(s::field)" in C++, but
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* C lacks the "::" operator.
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*/
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#define SIZEOF_FIELD(s, field) sizeof(((s *)NULL)->field)
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/**
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* This macro returns a member of the cvmx_bootmem_desc
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* structure. These members can't be directly addressed as
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* they might be in memory not directly reachable. In the case
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* where bootmem is compiled with LINUX_HOST, the structure
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* itself might be located on a remote Octeon. The argument
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* "field" is the member name of the cvmx_bootmem_desc to read.
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* Regardless of the type of the field, the return type is always
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* a u64.
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*/
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#define CVMX_BOOTMEM_DESC_GET_FIELD(oct, field) \
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__cvmx_bootmem_desc_get(oct, oct->bootmem_desc_addr, \
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offsetof(struct cvmx_bootmem_desc, field), \
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SIZEOF_FIELD(struct cvmx_bootmem_desc, field))
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#define __cvmx_bootmem_lock(flags)
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#define __cvmx_bootmem_unlock(flags)
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/**
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* This macro returns a member of the
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* cvmx_bootmem_named_block_desc structure. These members can't
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* be directly addressed as they might be in memory not directly
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* reachable. In the case where bootmem is compiled with
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* LINUX_HOST, the structure itself might be located on a remote
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* Octeon. The argument "field" is the member name of the
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* cvmx_bootmem_named_block_desc to read. Regardless of the type
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* of the field, the return type is always a u64. The "addr"
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* parameter is the physical address of the structure.
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*/
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#define CVMX_BOOTMEM_NAMED_GET_FIELD(oct, addr, field) \
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__cvmx_bootmem_desc_get(oct, addr, \
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offsetof(struct cvmx_bootmem_named_block_desc, field), \
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SIZEOF_FIELD(struct cvmx_bootmem_named_block_desc, field))
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/**
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* This function is the implementation of the get macros defined
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* for individual structure members. The argument are generated
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* by the macros inorder to read only the needed memory.
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*
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* @param oct Pointer to current octeon device
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* @param base 64bit physical address of the complete structure
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* @param offset Offset from the beginning of the structure to the member being
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* accessed.
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* @param size Size of the structure member.
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*
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* @return Value of the structure member promoted into a u64.
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*/
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static inline u64 __cvmx_bootmem_desc_get(struct octeon_device *oct,
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u64 base,
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u32 offset,
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u32 size)
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{
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base = (1ull << 63) | (base + offset);
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switch (size) {
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case 4:
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return octeon_read_device_mem32(oct, base);
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case 8:
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return octeon_read_device_mem64(oct, base);
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default:
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return 0;
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}
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}
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/**
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* This function retrieves the string name of a named block. It is
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* more complicated than a simple memcpy() since the named block
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* descriptor may not be directly accessible.
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*
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* @param addr Physical address of the named block descriptor
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* @param str String to receive the named block string name
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* @param len Length of the string buffer, which must match the length
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* stored in the bootmem descriptor.
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*/
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static void CVMX_BOOTMEM_NAMED_GET_NAME(struct octeon_device *oct,
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u64 addr,
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char *str,
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u32 len)
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{
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addr += offsetof(struct cvmx_bootmem_named_block_desc, name);
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octeon_pci_read_core_mem(oct, addr, str, len);
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str[len] = 0;
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}
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/* See header file for descriptions of functions */
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/**
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* Check the version information on the bootmem descriptor
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*
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* @param exact_match
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* Exact major version to check against. A zero means
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* check that the version supports named blocks.
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*
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* @return Zero if the version is correct. Negative if the version is
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* incorrect. Failures also cause a message to be displayed.
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*/
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static int __cvmx_bootmem_check_version(struct octeon_device *oct,
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u32 exact_match)
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{
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u32 major_version;
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u32 minor_version;
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if (!oct->bootmem_desc_addr)
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oct->bootmem_desc_addr =
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octeon_read_device_mem64(oct,
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BOOTLOADER_PCI_READ_DESC_ADDR);
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major_version =
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(u32)CVMX_BOOTMEM_DESC_GET_FIELD(oct, major_version);
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minor_version =
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(u32)CVMX_BOOTMEM_DESC_GET_FIELD(oct, minor_version);
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dev_dbg(&oct->pci_dev->dev, "%s: major_version=%d\n", __func__,
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major_version);
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if ((major_version > 3) ||
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(exact_match && major_version != exact_match)) {
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dev_err(&oct->pci_dev->dev, "bootmem ver mismatch %d.%d addr:0x%llx\n",
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major_version, minor_version,
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CAST_ULL(oct->bootmem_desc_addr));
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return -1;
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} else {
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return 0;
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}
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}
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static const struct cvmx_bootmem_named_block_desc
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*__cvmx_bootmem_find_named_block_flags(struct octeon_device *oct,
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const char *name, u32 flags)
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{
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struct cvmx_bootmem_named_block_desc *desc =
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&oct->bootmem_named_block_desc;
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u64 named_addr = cvmx_bootmem_phy_named_block_find(oct, name, flags);
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if (named_addr) {
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desc->base_addr = CVMX_BOOTMEM_NAMED_GET_FIELD(oct, named_addr,
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base_addr);
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desc->size =
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CVMX_BOOTMEM_NAMED_GET_FIELD(oct, named_addr, size);
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strncpy(desc->name, name, sizeof(desc->name));
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desc->name[sizeof(desc->name) - 1] = 0;
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return &oct->bootmem_named_block_desc;
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} else {
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return NULL;
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}
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}
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static u64 cvmx_bootmem_phy_named_block_find(struct octeon_device *oct,
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const char *name,
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u32 flags)
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{
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u64 result = 0;
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__cvmx_bootmem_lock(flags);
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if (!__cvmx_bootmem_check_version(oct, 3)) {
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u32 i;
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u64 named_block_array_addr =
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CVMX_BOOTMEM_DESC_GET_FIELD(oct,
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named_block_array_addr);
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u32 num_blocks = (u32)
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CVMX_BOOTMEM_DESC_GET_FIELD(oct, nb_num_blocks);
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u32 name_length = (u32)
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CVMX_BOOTMEM_DESC_GET_FIELD(oct, named_block_name_len);
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u64 named_addr = named_block_array_addr;
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for (i = 0; i < num_blocks; i++) {
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u64 named_size =
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CVMX_BOOTMEM_NAMED_GET_FIELD(oct, named_addr,
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size);
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if (name && named_size) {
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char *name_tmp =
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kmalloc(name_length + 1, GFP_KERNEL);
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CVMX_BOOTMEM_NAMED_GET_NAME(oct, named_addr,
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name_tmp,
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name_length);
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if (!strncmp(name, name_tmp, name_length)) {
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result = named_addr;
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kfree(name_tmp);
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break;
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}
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kfree(name_tmp);
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} else if (!name && !named_size) {
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result = named_addr;
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break;
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}
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named_addr +=
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sizeof(struct cvmx_bootmem_named_block_desc);
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}
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}
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__cvmx_bootmem_unlock(flags);
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return result;
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}
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/**
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* Find a named block on the remote Octeon
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*
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* @param name Name of block to find
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* @param base_addr Address the block is at (OUTPUT)
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* @param size The size of the block (OUTPUT)
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*
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* @return Zero on success, One on failure.
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*/
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static int octeon_named_block_find(struct octeon_device *oct, const char *name,
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u64 *base_addr, u64 *size)
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{
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const struct cvmx_bootmem_named_block_desc *named_block;
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octeon_remote_lock();
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named_block = __cvmx_bootmem_find_named_block_flags(oct, name, 0);
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octeon_remote_unlock();
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if (named_block) {
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*base_addr = named_block->base_addr;
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*size = named_block->size;
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return 0;
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}
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return 1;
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}
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static void octeon_remote_lock(void)
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{
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/* fill this in if any sharing is needed */
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}
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static void octeon_remote_unlock(void)
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{
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/* fill this in if any sharing is needed */
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}
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int octeon_console_send_cmd(struct octeon_device *oct, char *cmd_str,
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u32 wait_hundredths)
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{
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u32 len = strlen(cmd_str);
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dev_dbg(&oct->pci_dev->dev, "sending \"%s\" to bootloader\n", cmd_str);
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if (len > BOOTLOADER_PCI_WRITE_BUFFER_STR_LEN - 1) {
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dev_err(&oct->pci_dev->dev, "Command string too long, max length is: %d\n",
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BOOTLOADER_PCI_WRITE_BUFFER_STR_LEN - 1);
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return -1;
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}
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if (octeon_wait_for_bootloader(oct, wait_hundredths) != 0) {
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dev_err(&oct->pci_dev->dev, "Bootloader not ready for command.\n");
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return -1;
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}
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/* Write command to bootloader */
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octeon_remote_lock();
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octeon_pci_write_core_mem(oct, BOOTLOADER_PCI_READ_BUFFER_DATA_ADDR,
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(u8 *)cmd_str, len);
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octeon_write_device_mem32(oct, BOOTLOADER_PCI_READ_BUFFER_LEN_ADDR,
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len);
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octeon_write_device_mem32(oct, BOOTLOADER_PCI_READ_BUFFER_OWNER_ADDR,
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OCTEON_PCI_IO_BUF_OWNER_OCTEON);
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/* Bootloader should accept command very quickly
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* if it really was ready
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*/
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if (octeon_wait_for_bootloader(oct, 200) != 0) {
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octeon_remote_unlock();
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dev_err(&oct->pci_dev->dev, "Bootloader did not accept command.\n");
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return -1;
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}
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octeon_remote_unlock();
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return 0;
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}
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int octeon_wait_for_bootloader(struct octeon_device *oct,
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u32 wait_time_hundredths)
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{
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dev_dbg(&oct->pci_dev->dev, "waiting %d0 ms for bootloader\n",
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wait_time_hundredths);
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if (octeon_mem_access_ok(oct))
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return -1;
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while (wait_time_hundredths > 0 &&
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octeon_read_device_mem32(oct,
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BOOTLOADER_PCI_READ_BUFFER_OWNER_ADDR)
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!= OCTEON_PCI_IO_BUF_OWNER_HOST) {
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if (--wait_time_hundredths <= 0)
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return -1;
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schedule_timeout_uninterruptible(HZ / 100);
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}
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return 0;
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}
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static void octeon_console_handle_result(struct octeon_device *oct,
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size_t console_num,
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char *buffer, s32 bytes_read)
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{
|
|
struct octeon_console *console;
|
|
|
|
console = &oct->console[console_num];
|
|
|
|
console->waiting = 0;
|
|
}
|
|
|
|
static char console_buffer[OCTEON_CONSOLE_MAX_READ_BYTES];
|
|
|
|
static void output_console_line(struct octeon_device *oct,
|
|
struct octeon_console *console,
|
|
size_t console_num,
|
|
char *console_buffer,
|
|
s32 bytes_read)
|
|
{
|
|
char *line;
|
|
s32 i;
|
|
|
|
line = console_buffer;
|
|
for (i = 0; i < bytes_read; i++) {
|
|
/* Output a line at a time, prefixed */
|
|
if (console_buffer[i] == '\n') {
|
|
console_buffer[i] = '\0';
|
|
if (console->leftover[0]) {
|
|
dev_info(&oct->pci_dev->dev, "%lu: %s%s\n",
|
|
console_num, console->leftover,
|
|
line);
|
|
console->leftover[0] = '\0';
|
|
} else {
|
|
dev_info(&oct->pci_dev->dev, "%lu: %s\n",
|
|
console_num, line);
|
|
}
|
|
line = &console_buffer[i + 1];
|
|
}
|
|
}
|
|
|
|
/* Save off any leftovers */
|
|
if (line != &console_buffer[bytes_read]) {
|
|
console_buffer[bytes_read] = '\0';
|
|
strcpy(console->leftover, line);
|
|
}
|
|
}
|
|
|
|
static void check_console(struct work_struct *work)
|
|
{
|
|
s32 bytes_read, tries, total_read;
|
|
struct octeon_console *console;
|
|
struct cavium_wk *wk = (struct cavium_wk *)work;
|
|
struct octeon_device *oct = (struct octeon_device *)wk->ctxptr;
|
|
size_t console_num = wk->ctxul;
|
|
u32 delay;
|
|
|
|
console = &oct->console[console_num];
|
|
tries = 0;
|
|
total_read = 0;
|
|
|
|
do {
|
|
/* Take console output regardless of whether it will
|
|
* be logged
|
|
*/
|
|
bytes_read =
|
|
octeon_console_read(oct, console_num, console_buffer,
|
|
sizeof(console_buffer) - 1, 0);
|
|
if (bytes_read > 0) {
|
|
total_read += bytes_read;
|
|
if (console->waiting) {
|
|
octeon_console_handle_result(oct, console_num,
|
|
console_buffer,
|
|
bytes_read);
|
|
}
|
|
if (octeon_console_debug_enabled(console_num)) {
|
|
output_console_line(oct, console, console_num,
|
|
console_buffer, bytes_read);
|
|
}
|
|
} else if (bytes_read < 0) {
|
|
dev_err(&oct->pci_dev->dev, "Error reading console %lu, ret=%d\n",
|
|
console_num, bytes_read);
|
|
}
|
|
|
|
tries++;
|
|
} while ((bytes_read > 0) && (tries < 16));
|
|
|
|
/* If nothing is read after polling the console,
|
|
* output any leftovers if any
|
|
*/
|
|
if (octeon_console_debug_enabled(console_num) &&
|
|
(total_read == 0) && (console->leftover[0])) {
|
|
dev_info(&oct->pci_dev->dev, "%lu: %s\n",
|
|
console_num, console->leftover);
|
|
console->leftover[0] = '\0';
|
|
}
|
|
|
|
delay = OCTEON_CONSOLE_POLL_INTERVAL_MS;
|
|
|
|
schedule_delayed_work(&wk->work, msecs_to_jiffies(delay));
|
|
}
|
|
|
|
int octeon_init_consoles(struct octeon_device *oct)
|
|
{
|
|
int ret = 0;
|
|
u64 addr, size;
|
|
|
|
ret = octeon_mem_access_ok(oct);
|
|
if (ret) {
|
|
dev_err(&oct->pci_dev->dev, "Memory access not okay'\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = octeon_named_block_find(oct, OCTEON_PCI_CONSOLE_BLOCK_NAME, &addr,
|
|
&size);
|
|
if (ret) {
|
|
dev_err(&oct->pci_dev->dev, "Could not find console '%s'\n",
|
|
OCTEON_PCI_CONSOLE_BLOCK_NAME);
|
|
return ret;
|
|
}
|
|
|
|
/* num_consoles > 0, is an indication that the consoles
|
|
* are accessible
|
|
*/
|
|
oct->num_consoles = octeon_read_device_mem32(oct,
|
|
addr + offsetof(struct octeon_pci_console_desc,
|
|
num_consoles));
|
|
oct->console_desc_addr = addr;
|
|
|
|
dev_dbg(&oct->pci_dev->dev, "Initialized consoles. %d available\n",
|
|
oct->num_consoles);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int octeon_add_console(struct octeon_device *oct, u32 console_num)
|
|
{
|
|
int ret = 0;
|
|
u32 delay;
|
|
u64 coreaddr;
|
|
struct delayed_work *work;
|
|
struct octeon_console *console;
|
|
|
|
if (console_num >= oct->num_consoles) {
|
|
dev_err(&oct->pci_dev->dev,
|
|
"trying to read from console number %d when only 0 to %d exist\n",
|
|
console_num, oct->num_consoles);
|
|
} else {
|
|
console = &oct->console[console_num];
|
|
|
|
console->waiting = 0;
|
|
|
|
coreaddr = oct->console_desc_addr + console_num * 8 +
|
|
offsetof(struct octeon_pci_console_desc,
|
|
console_addr_array);
|
|
console->addr = octeon_read_device_mem64(oct, coreaddr);
|
|
coreaddr = console->addr + offsetof(struct octeon_pci_console,
|
|
buf_size);
|
|
console->buffer_size = octeon_read_device_mem32(oct, coreaddr);
|
|
coreaddr = console->addr + offsetof(struct octeon_pci_console,
|
|
input_base_addr);
|
|
console->input_base_addr =
|
|
octeon_read_device_mem64(oct, coreaddr);
|
|
coreaddr = console->addr + offsetof(struct octeon_pci_console,
|
|
output_base_addr);
|
|
console->output_base_addr =
|
|
octeon_read_device_mem64(oct, coreaddr);
|
|
console->leftover[0] = '\0';
|
|
|
|
work = &oct->console_poll_work[console_num].work;
|
|
|
|
INIT_DELAYED_WORK(work, check_console);
|
|
oct->console_poll_work[console_num].ctxptr = (void *)oct;
|
|
oct->console_poll_work[console_num].ctxul = console_num;
|
|
delay = OCTEON_CONSOLE_POLL_INTERVAL_MS;
|
|
schedule_delayed_work(work, msecs_to_jiffies(delay));
|
|
|
|
if (octeon_console_debug_enabled(console_num)) {
|
|
ret = octeon_console_send_cmd(oct,
|
|
"setenv pci_console_active 1",
|
|
2000);
|
|
}
|
|
|
|
console->active = 1;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* Removes all consoles
|
|
*
|
|
* @param oct octeon device
|
|
*/
|
|
void octeon_remove_consoles(struct octeon_device *oct)
|
|
{
|
|
u32 i;
|
|
struct octeon_console *console;
|
|
|
|
for (i = 0; i < oct->num_consoles; i++) {
|
|
console = &oct->console[i];
|
|
|
|
if (!console->active)
|
|
continue;
|
|
|
|
cancel_delayed_work_sync(&oct->console_poll_work[i].
|
|
work);
|
|
console->addr = 0;
|
|
console->buffer_size = 0;
|
|
console->input_base_addr = 0;
|
|
console->output_base_addr = 0;
|
|
}
|
|
|
|
oct->num_consoles = 0;
|
|
}
|
|
|
|
static inline int octeon_console_free_bytes(u32 buffer_size,
|
|
u32 wr_idx,
|
|
u32 rd_idx)
|
|
{
|
|
if (rd_idx >= buffer_size || wr_idx >= buffer_size)
|
|
return -1;
|
|
|
|
return ((buffer_size - 1) - (wr_idx - rd_idx)) % buffer_size;
|
|
}
|
|
|
|
static inline int octeon_console_avail_bytes(u32 buffer_size,
|
|
u32 wr_idx,
|
|
u32 rd_idx)
|
|
{
|
|
if (rd_idx >= buffer_size || wr_idx >= buffer_size)
|
|
return -1;
|
|
|
|
return buffer_size - 1 -
|
|
octeon_console_free_bytes(buffer_size, wr_idx, rd_idx);
|
|
}
|
|
|
|
int octeon_console_read(struct octeon_device *oct, u32 console_num,
|
|
char *buffer, u32 buf_size, u32 flags)
|
|
{
|
|
int bytes_to_read;
|
|
u32 rd_idx, wr_idx;
|
|
struct octeon_console *console;
|
|
|
|
if (console_num >= oct->num_consoles) {
|
|
dev_err(&oct->pci_dev->dev, "Attempted to read from disabled console %d\n",
|
|
console_num);
|
|
return 0;
|
|
}
|
|
|
|
console = &oct->console[console_num];
|
|
|
|
/* Check to see if any data is available.
|
|
* Maybe optimize this with 64-bit read.
|
|
*/
|
|
rd_idx = octeon_read_device_mem32(oct, console->addr +
|
|
offsetof(struct octeon_pci_console, output_read_index));
|
|
wr_idx = octeon_read_device_mem32(oct, console->addr +
|
|
offsetof(struct octeon_pci_console, output_write_index));
|
|
|
|
bytes_to_read = octeon_console_avail_bytes(console->buffer_size,
|
|
wr_idx, rd_idx);
|
|
if (bytes_to_read <= 0)
|
|
return bytes_to_read;
|
|
|
|
bytes_to_read = MIN(bytes_to_read, (s32)buf_size);
|
|
|
|
/* Check to see if what we want to read is not contiguous, and limit
|
|
* ourselves to the contiguous block
|
|
*/
|
|
if (rd_idx + bytes_to_read >= console->buffer_size)
|
|
bytes_to_read = console->buffer_size - rd_idx;
|
|
|
|
octeon_pci_read_core_mem(oct, console->output_base_addr + rd_idx,
|
|
buffer, bytes_to_read);
|
|
octeon_write_device_mem32(oct, console->addr +
|
|
offsetof(struct octeon_pci_console,
|
|
output_read_index),
|
|
(rd_idx + bytes_to_read) %
|
|
console->buffer_size);
|
|
|
|
return bytes_to_read;
|
|
}
|