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Following patch V8 adds support for Cavium Liquidio pci express based 10Gig ethernet adapters. 1) Consolidated all debug macros to either call dev_* or netdev_* macros directly, feedback from previous patch. 2) Changed soft commands to avoid crash when running in interrupt context. 3) Fixed link status not reflecting correct status when NetworkManager is running. Added MODULE_FIRMWARE declarations. Following were the previous patches. Patch V7: 1) Minor comments from v6 release regarding debug statements. 2) Fix for large multicast lists. 3) Fixed lockup issue if port initialization fails. 4) Enabled MSI by default. https://patchwork.ozlabs.org/patch/464441/ Patch V6: 1) Addressed the uint64 vs u64 issue, feedback from previous patch. 2) Consolidated some receive processing routines. 3) Removed link status polling method. https://patchwork.ozlabs.org/patch/459514/ Patch V5: Based on the feedback from earlier patches with regards to consolidation of common functions like device init, register programming for cn66xx and cn68xx devices. https://patchwork.ozlabs.org/patch/438979/ Patch V4: Following were the changes based on the feedback from earlier patch: 1) Added mmiowb while synchronizing queue updates and other hw interactions. 2) Statistics will now be incremented non-atomically per each ring. liquidio_get_stats will add stats of each ring while reporting the total statistics counts. 3) Modified liquidio_ioctl to return proper return codes. 4) Modified device naming to use standard Ethernet naming. 5) Global function names in the driver will have lio_/liquidio_/octeon_ prefix. 6) Ethtool related changes for: Removed redundant stats and jiffies. Use default ethtool handler of link status. Speed setting will make use of ethtool_cmd_speed_set. 7) Added checks for pci_map_* return codes. 8) Check for signals while waiting in interruptible mode https://patchwork.ozlabs.org/patch/435073/ Patch v3: Implemented feedback from previous patch like: Removed NAPI Config and DEBUG config options, added BQL and xmit_more support. https://patchwork.ozlabs.org/patch/422749/ Patch V2: Implemented feedback from previous patch. https://patchwork.ozlabs.org/patch/413539/ First Patch: https://patchwork.ozlabs.org/patch/412946/ Signed-off-by: Derek Chickles <derek.chickles@caviumnetworks.com> Signed-off-by: Satanand Burla <satananda.burla@caviumnetworks.com> Signed-off-by: Felix Manlunas <felix.manlunas@caviumnetworks.com> Signed-off-by: Robert Richter <Robert.Richter@caviumnetworks.com> Signed-off-by: Aleksey Makarov <Aleksey.Makarov@caviumnetworks.com> Signed-off-by: Raghu Vatsavayi <raghu.vatsavayi@caviumnetworks.com> Signed-off-by: David S. Miller <davem@davemloft.net>
108 lines
3.9 KiB
C
108 lines
3.9 KiB
C
/**********************************************************************
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* Author: Cavium, Inc.
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*
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* Contact: support@cavium.com
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* Please include "LiquidIO" in the subject.
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*
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* Copyright (c) 2003-2015 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium, Inc. for more information
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**********************************************************************/
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/*! \file cn66xx_device.h
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* \brief Host Driver: Routines that perform CN66XX specific operations.
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*/
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#ifndef __CN66XX_DEVICE_H__
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#define __CN66XX_DEVICE_H__
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/* Register address and configuration for a CN6XXX devices.
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* If device specific changes need to be made then add a struct to include
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* device specific fields as shown in the commented section
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*/
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struct octeon_cn6xxx {
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/** PCI interrupt summary register */
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u8 __iomem *intr_sum_reg64;
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/** PCI interrupt enable register */
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u8 __iomem *intr_enb_reg64;
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/** The PCI interrupt mask used by interrupt handler */
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u64 intr_mask64;
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struct octeon_config *conf;
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/* Example additional fields - not used currently
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* struct {
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* }cn6xyz;
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*/
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/* For the purpose of atomic access to interrupt enable reg */
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spinlock_t lock_for_droq_int_enb_reg;
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};
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enum octeon_pcie_mps {
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PCIE_MPS_DEFAULT = -1, /* Use the default setup by BIOS */
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PCIE_MPS_128B = 0,
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PCIE_MPS_256B = 1
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};
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enum octeon_pcie_mrrs {
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PCIE_MRRS_DEFAULT = -1, /* Use the default setup by BIOS */
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PCIE_MRRS_128B = 0,
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PCIE_MRRS_256B = 1,
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PCIE_MRRS_512B = 2,
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PCIE_MRRS_1024B = 3,
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PCIE_MRRS_2048B = 4,
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PCIE_MRRS_4096B = 5
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};
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/* Common functions for 66xx and 68xx */
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int lio_cn6xxx_soft_reset(struct octeon_device *oct);
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void lio_cn6xxx_enable_error_reporting(struct octeon_device *oct);
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void lio_cn6xxx_setup_pcie_mps(struct octeon_device *oct,
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enum octeon_pcie_mps mps);
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void lio_cn6xxx_setup_pcie_mrrs(struct octeon_device *oct,
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enum octeon_pcie_mrrs mrrs);
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void lio_cn6xxx_setup_global_input_regs(struct octeon_device *oct);
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void lio_cn6xxx_setup_global_output_regs(struct octeon_device *oct);
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void lio_cn6xxx_setup_iq_regs(struct octeon_device *oct, u32 iq_no);
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void lio_cn6xxx_setup_oq_regs(struct octeon_device *oct, u32 oq_no);
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void lio_cn6xxx_enable_io_queues(struct octeon_device *oct);
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void lio_cn6xxx_disable_io_queues(struct octeon_device *oct);
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void lio_cn6xxx_process_pcie_error_intr(struct octeon_device *oct, u64 intr64);
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int lio_cn6xxx_process_droq_intr_regs(struct octeon_device *oct);
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irqreturn_t lio_cn6xxx_process_interrupt_regs(void *dev);
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void lio_cn6xxx_reinit_regs(struct octeon_device *oct);
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void lio_cn6xxx_bar1_idx_setup(struct octeon_device *oct, u64 core_addr,
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u32 idx, int valid);
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void lio_cn6xxx_bar1_idx_write(struct octeon_device *oct, u32 idx, u32 mask);
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u32 lio_cn6xxx_bar1_idx_read(struct octeon_device *oct, u32 idx);
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u32
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lio_cn6xxx_update_read_index(struct octeon_device *oct __attribute__((unused)),
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struct octeon_instr_queue *iq);
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void lio_cn6xxx_enable_interrupt(void *chip);
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void lio_cn6xxx_disable_interrupt(void *chip);
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void cn6xxx_get_pcie_qlmport(struct octeon_device *oct);
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void lio_cn6xxx_setup_reg_address(struct octeon_device *oct, void *chip,
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struct octeon_reg_list *reg_list);
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u32 lio_cn6xxx_coprocessor_clock(struct octeon_device *oct);
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u32 lio_cn6xxx_get_oq_ticks(struct octeon_device *oct, u32 time_intr_in_us);
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int lio_setup_cn66xx_octeon_device(struct octeon_device *);
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int lio_validate_cn6xxx_config_info(struct octeon_device *oct,
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struct octeon_config *);
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#endif
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