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43c3473552
In yenta_socket, we default to using the resource setting of the CardBus bridge. However, this is a PCI-bus-centric view of resources and thus needs to be converted to generic resources first. Therefore, add a call to pcibios_bus_to_resource() call in between. This function is a mere wrapper on x86 and friends, however on some others it already exists, is added in this patch (alpha, arm, ppc, ppc64) or still needs to be provided (parisc -- where is its pcibios_resource_to_bus() ?). Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
986 lines
25 KiB
C
986 lines
25 KiB
C
/*
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* Port for PPC64 David Engebretsen, IBM Corp.
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* Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
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*
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* Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
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* Rework, based on alpha PCI code.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#undef DEBUG
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <linux/mm.h>
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#include <linux/list.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#include <asm/byteorder.h>
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#include <asm/irq.h>
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#include <asm/machdep.h>
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#include <asm/udbg.h>
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#include "pci.h"
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#ifdef DEBUG
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#define DBG(fmt...) udbg_printf(fmt)
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#else
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#define DBG(fmt...)
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#endif
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unsigned long pci_probe_only = 1;
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unsigned long pci_assign_all_buses = 0;
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/*
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* legal IO pages under MAX_ISA_PORT. This is to ensure we don't touch
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* devices we don't have access to.
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*/
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unsigned long io_page_mask;
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EXPORT_SYMBOL(io_page_mask);
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unsigned int pcibios_assign_all_busses(void)
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{
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return pci_assign_all_buses;
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}
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/* pci_io_base -- the base address from which io bars are offsets.
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* This is the lowest I/O base address (so bar values are always positive),
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* and it *must* be the start of ISA space if an ISA bus exists because
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* ISA drivers use hard coded offsets. If no ISA bus exists a dummy
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* page is mapped and isa_io_limit prevents access to it.
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*/
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unsigned long isa_io_base; /* NULL if no ISA bus */
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EXPORT_SYMBOL(isa_io_base);
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unsigned long pci_io_base;
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EXPORT_SYMBOL(pci_io_base);
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void iSeries_pcibios_init(void);
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LIST_HEAD(hose_list);
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struct dma_mapping_ops pci_dma_ops;
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EXPORT_SYMBOL(pci_dma_ops);
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int global_phb_number; /* Global phb counter */
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/* Cached ISA bridge dev. */
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struct pci_dev *ppc64_isabridge_dev = NULL;
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static void fixup_broken_pcnet32(struct pci_dev* dev)
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{
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if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
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dev->vendor = PCI_VENDOR_ID_AMD;
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pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
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pci_name_device(dev);
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
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void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
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struct resource *res)
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{
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unsigned long offset = 0;
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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if (!hose)
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return;
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if (res->flags & IORESOURCE_IO)
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offset = (unsigned long)hose->io_base_virt - pci_io_base;
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if (res->flags & IORESOURCE_MEM)
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offset = hose->pci_mem_offset;
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region->start = res->start - offset;
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region->end = res->end - offset;
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}
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void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
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struct pci_bus_region *region)
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{
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unsigned long offset = 0;
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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if (!hose)
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return;
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if (res->flags & IORESOURCE_IO)
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offset = (unsigned long)hose->io_base_virt - pci_io_base;
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if (res->flags & IORESOURCE_MEM)
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offset = hose->pci_mem_offset;
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res->start = region->start + offset;
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res->end = region->end + offset;
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}
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#ifdef CONFIG_HOTPLUG
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EXPORT_SYMBOL(pcibios_resource_to_bus);
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EXPORT_SYMBOL(pcibios_bus_to_resource);
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#endif
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/*
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* We need to avoid collisions with `mirrored' VGA ports
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* and other strange ISA hardware, so we always want the
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* addresses to be allocated in the 0x000-0x0ff region
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* modulo 0x400.
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*
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* Why? Because some silly external IO cards only decode
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* the low 10 bits of the IO address. The 0x00-0xff region
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* is reserved for motherboard devices that decode all 16
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* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
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* but we want to try to avoid allocating at 0x2900-0x2bff
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* which might have be mirrored at 0x0100-0x03ff..
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*/
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void pcibios_align_resource(void *data, struct resource *res,
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unsigned long size, unsigned long align)
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{
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struct pci_dev *dev = data;
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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unsigned long start = res->start;
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unsigned long alignto;
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if (res->flags & IORESOURCE_IO) {
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unsigned long offset = (unsigned long)hose->io_base_virt -
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pci_io_base;
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/* Make sure we start at our min on all hoses */
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if (start - offset < PCIBIOS_MIN_IO)
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start = PCIBIOS_MIN_IO + offset;
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/*
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* Put everything into 0x00-0xff region modulo 0x400
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*/
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if (start & 0x300)
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start = (start + 0x3ff) & ~0x3ff;
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} else if (res->flags & IORESOURCE_MEM) {
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/* Make sure we start at our min on all hoses */
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if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM)
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start = PCIBIOS_MIN_MEM + hose->pci_mem_offset;
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/* Align to multiple of size of minimum base. */
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alignto = max(0x1000UL, align);
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start = ALIGN(start, alignto);
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}
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res->start = start;
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}
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static DEFINE_SPINLOCK(hose_spinlock);
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/*
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* pci_controller(phb) initialized common variables.
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*/
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void __devinit pci_setup_pci_controller(struct pci_controller *hose)
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{
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memset(hose, 0, sizeof(struct pci_controller));
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spin_lock(&hose_spinlock);
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hose->global_number = global_phb_number++;
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list_add_tail(&hose->list_node, &hose_list);
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spin_unlock(&hose_spinlock);
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}
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static void __init pcibios_claim_one_bus(struct pci_bus *b)
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{
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struct pci_dev *dev;
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struct pci_bus *child_bus;
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list_for_each_entry(dev, &b->devices, bus_list) {
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int i;
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for (i = 0; i < PCI_NUM_RESOURCES; i++) {
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struct resource *r = &dev->resource[i];
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if (r->parent || !r->start || !r->flags)
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continue;
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pci_claim_resource(dev, i);
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}
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}
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list_for_each_entry(child_bus, &b->children, node)
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pcibios_claim_one_bus(child_bus);
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}
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#ifndef CONFIG_PPC_ISERIES
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static void __init pcibios_claim_of_setup(void)
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{
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struct pci_bus *b;
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list_for_each_entry(b, &pci_root_buses, node)
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pcibios_claim_one_bus(b);
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}
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#endif
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static int __init pcibios_init(void)
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{
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struct pci_controller *hose, *tmp;
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struct pci_bus *bus;
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/* For now, override phys_mem_access_prot. If we need it,
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* later, we may move that initialization to each ppc_md
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*/
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ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
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#ifdef CONFIG_PPC_ISERIES
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iSeries_pcibios_init();
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#endif
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printk("PCI: Probing PCI hardware\n");
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/* Scan all of the recorded PCI controllers. */
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list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
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hose->last_busno = 0xff;
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bus = pci_scan_bus(hose->first_busno, hose->ops,
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hose->arch_data);
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hose->bus = bus;
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hose->last_busno = bus->subordinate;
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}
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#ifndef CONFIG_PPC_ISERIES
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if (pci_probe_only)
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pcibios_claim_of_setup();
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else
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/* FIXME: `else' will be removed when
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pci_assign_unassigned_resources() is able to work
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correctly with [partially] allocated PCI tree. */
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pci_assign_unassigned_resources();
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#endif /* !CONFIG_PPC_ISERIES */
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/* Call machine dependent final fixup */
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if (ppc_md.pcibios_fixup)
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ppc_md.pcibios_fixup();
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/* Cache the location of the ISA bridge (if we have one) */
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ppc64_isabridge_dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
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if (ppc64_isabridge_dev != NULL)
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printk("ISA bridge at %s\n", pci_name(ppc64_isabridge_dev));
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printk("PCI: Probing PCI hardware done\n");
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return 0;
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}
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subsys_initcall(pcibios_init);
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char __init *pcibios_setup(char *str)
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{
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return str;
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}
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int pcibios_enable_device(struct pci_dev *dev, int mask)
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{
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u16 cmd, oldcmd;
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int i;
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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oldcmd = cmd;
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for (i = 0; i < PCI_NUM_RESOURCES; i++) {
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struct resource *res = &dev->resource[i];
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/* Only set up the requested stuff */
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if (!(mask & (1<<i)))
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continue;
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if (res->flags & IORESOURCE_IO)
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cmd |= PCI_COMMAND_IO;
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if (res->flags & IORESOURCE_MEM)
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cmd |= PCI_COMMAND_MEMORY;
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}
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if (cmd != oldcmd) {
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printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
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pci_name(dev), cmd);
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/* Enable the appropriate bits in the PCI command register. */
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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}
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return 0;
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}
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/*
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* Return the domain number for this bus.
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*/
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int pci_domain_nr(struct pci_bus *bus)
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{
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#ifdef CONFIG_PPC_ISERIES
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return 0;
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#else
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struct pci_controller *hose = pci_bus_to_host(bus);
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return hose->global_number;
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#endif
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}
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EXPORT_SYMBOL(pci_domain_nr);
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/* Decide whether to display the domain number in /proc */
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int pci_proc_domain(struct pci_bus *bus)
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{
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#ifdef CONFIG_PPC_ISERIES
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return 0;
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#else
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struct pci_controller *hose = pci_bus_to_host(bus);
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return hose->buid;
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#endif
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}
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/*
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* Platform support for /proc/bus/pci/X/Y mmap()s,
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* modelled on the sparc64 implementation by Dave Miller.
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* -- paulus.
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*/
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/*
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* Adjust vm_pgoff of VMA such that it is the physical page offset
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* corresponding to the 32-bit pci bus offset for DEV requested by the user.
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*
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* Basically, the user finds the base address for his device which he wishes
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* to mmap. They read the 32-bit value from the config space base register,
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* add whatever PAGE_SIZE multiple offset they wish, and feed this into the
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* offset parameter of mmap on /proc/bus/pci/XXX for that device.
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*
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* Returns negative error code on failure, zero on success.
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*/
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static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
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unsigned long *offset,
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enum pci_mmap_state mmap_state)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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unsigned long io_offset = 0;
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int i, res_bit;
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if (hose == 0)
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return NULL; /* should never happen */
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/* If memory, add on the PCI bridge address offset */
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if (mmap_state == pci_mmap_mem) {
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*offset += hose->pci_mem_offset;
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res_bit = IORESOURCE_MEM;
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} else {
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io_offset = (unsigned long)hose->io_base_virt - pci_io_base;
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*offset += io_offset;
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res_bit = IORESOURCE_IO;
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}
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/*
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* Check that the offset requested corresponds to one of the
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* resources of the device.
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*/
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for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
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struct resource *rp = &dev->resource[i];
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int flags = rp->flags;
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/* treat ROM as memory (should be already) */
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if (i == PCI_ROM_RESOURCE)
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flags |= IORESOURCE_MEM;
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/* Active and same type? */
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if ((flags & res_bit) == 0)
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continue;
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/* In the range of this resource? */
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if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
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continue;
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/* found it! construct the final physical address */
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if (mmap_state == pci_mmap_io)
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*offset += hose->io_base_phys - io_offset;
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return rp;
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}
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return NULL;
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}
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/*
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* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
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* device mapping.
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*/
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static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
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pgprot_t protection,
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enum pci_mmap_state mmap_state,
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int write_combine)
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{
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unsigned long prot = pgprot_val(protection);
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/* Write combine is always 0 on non-memory space mappings. On
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* memory space, if the user didn't pass 1, we check for a
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* "prefetchable" resource. This is a bit hackish, but we use
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* this to workaround the inability of /sysfs to provide a write
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* combine bit
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*/
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if (mmap_state != pci_mmap_mem)
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write_combine = 0;
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else if (write_combine == 0) {
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if (rp->flags & IORESOURCE_PREFETCH)
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write_combine = 1;
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}
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/* XXX would be nice to have a way to ask for write-through */
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prot |= _PAGE_NO_CACHE;
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if (write_combine)
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prot &= ~_PAGE_GUARDED;
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else
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prot |= _PAGE_GUARDED;
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printk("PCI map for %s:%lx, prot: %lx\n", pci_name(dev), rp->start,
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prot);
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return __pgprot(prot);
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}
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/*
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* This one is used by /dev/mem and fbdev who have no clue about the
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* PCI device, it tries to find the PCI device first and calls the
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* above routine
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*/
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pgprot_t pci_phys_mem_access_prot(struct file *file,
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unsigned long offset,
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unsigned long size,
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pgprot_t protection)
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{
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struct pci_dev *pdev = NULL;
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struct resource *found = NULL;
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unsigned long prot = pgprot_val(protection);
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int i;
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if (page_is_ram(offset >> PAGE_SHIFT))
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return __pgprot(prot);
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prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
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for_each_pci_dev(pdev) {
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for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
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struct resource *rp = &pdev->resource[i];
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int flags = rp->flags;
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/* Active and same type? */
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if ((flags & IORESOURCE_MEM) == 0)
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continue;
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/* In the range of this resource? */
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if (offset < (rp->start & PAGE_MASK) ||
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offset > rp->end)
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continue;
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found = rp;
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break;
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}
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if (found)
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break;
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}
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if (found) {
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if (found->flags & IORESOURCE_PREFETCH)
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prot &= ~_PAGE_GUARDED;
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pci_dev_put(pdev);
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}
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DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
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return __pgprot(prot);
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}
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|
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/*
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* Perform the actual remap of the pages for a PCI device mapping, as
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* appropriate for this architecture. The region in the process to map
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* is described by vm_start and vm_end members of VMA, the base physical
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* address is found in vm_pgoff.
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* The pci device structure is provided so that architectures may make mapping
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* decisions on a per-device or per-bus basis.
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*
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* Returns a negative error code on failure, zero on success.
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*/
|
|
int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
|
|
enum pci_mmap_state mmap_state,
|
|
int write_combine)
|
|
{
|
|
unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
|
|
struct resource *rp;
|
|
int ret;
|
|
|
|
rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
|
|
if (rp == NULL)
|
|
return -EINVAL;
|
|
|
|
vma->vm_pgoff = offset >> PAGE_SHIFT;
|
|
vma->vm_flags |= VM_SHM | VM_LOCKED | VM_IO;
|
|
vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
|
|
vma->vm_page_prot,
|
|
mmap_state, write_combine);
|
|
|
|
ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
|
|
vma->vm_end - vma->vm_start, vma->vm_page_prot);
|
|
|
|
return ret;
|
|
}
|
|
|
|
#ifdef CONFIG_PPC_MULTIPLATFORM
|
|
static ssize_t pci_show_devspec(struct device *dev, struct device_attribute *attr, char *buf)
|
|
{
|
|
struct pci_dev *pdev;
|
|
struct device_node *np;
|
|
|
|
pdev = to_pci_dev (dev);
|
|
np = pci_device_to_OF_node(pdev);
|
|
if (np == NULL || np->full_name == NULL)
|
|
return 0;
|
|
return sprintf(buf, "%s", np->full_name);
|
|
}
|
|
static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
|
|
#endif /* CONFIG_PPC_MULTIPLATFORM */
|
|
|
|
void pcibios_add_platform_entries(struct pci_dev *pdev)
|
|
{
|
|
#ifdef CONFIG_PPC_MULTIPLATFORM
|
|
device_create_file(&pdev->dev, &dev_attr_devspec);
|
|
#endif /* CONFIG_PPC_MULTIPLATFORM */
|
|
}
|
|
|
|
#ifdef CONFIG_PPC_MULTIPLATFORM
|
|
|
|
#define ISA_SPACE_MASK 0x1
|
|
#define ISA_SPACE_IO 0x1
|
|
|
|
static void __devinit pci_process_ISA_OF_ranges(struct device_node *isa_node,
|
|
unsigned long phb_io_base_phys,
|
|
void __iomem * phb_io_base_virt)
|
|
{
|
|
struct isa_range *range;
|
|
unsigned long pci_addr;
|
|
unsigned int isa_addr;
|
|
unsigned int size;
|
|
int rlen = 0;
|
|
|
|
range = (struct isa_range *) get_property(isa_node, "ranges", &rlen);
|
|
if (range == NULL || (rlen < sizeof(struct isa_range))) {
|
|
printk(KERN_ERR "no ISA ranges or unexpected isa range size,"
|
|
"mapping 64k\n");
|
|
__ioremap_explicit(phb_io_base_phys,
|
|
(unsigned long)phb_io_base_virt,
|
|
0x10000, _PAGE_NO_CACHE | _PAGE_GUARDED);
|
|
return;
|
|
}
|
|
|
|
/* From "ISA Binding to 1275"
|
|
* The ranges property is laid out as an array of elements,
|
|
* each of which comprises:
|
|
* cells 0 - 1: an ISA address
|
|
* cells 2 - 4: a PCI address
|
|
* (size depending on dev->n_addr_cells)
|
|
* cell 5: the size of the range
|
|
*/
|
|
if ((range->isa_addr.a_hi && ISA_SPACE_MASK) == ISA_SPACE_IO) {
|
|
isa_addr = range->isa_addr.a_lo;
|
|
pci_addr = (unsigned long) range->pci_addr.a_mid << 32 |
|
|
range->pci_addr.a_lo;
|
|
|
|
/* Assume these are both zero */
|
|
if ((pci_addr != 0) || (isa_addr != 0)) {
|
|
printk(KERN_ERR "unexpected isa to pci mapping: %s\n",
|
|
__FUNCTION__);
|
|
return;
|
|
}
|
|
|
|
size = PAGE_ALIGN(range->size);
|
|
|
|
__ioremap_explicit(phb_io_base_phys,
|
|
(unsigned long) phb_io_base_virt,
|
|
size, _PAGE_NO_CACHE | _PAGE_GUARDED);
|
|
}
|
|
}
|
|
|
|
void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
|
|
struct device_node *dev)
|
|
{
|
|
unsigned int *ranges;
|
|
unsigned long size;
|
|
int rlen = 0;
|
|
int memno = 0;
|
|
struct resource *res;
|
|
int np, na = prom_n_addr_cells(dev);
|
|
unsigned long pci_addr, cpu_phys_addr;
|
|
|
|
np = na + 5;
|
|
|
|
/* From "PCI Binding to 1275"
|
|
* The ranges property is laid out as an array of elements,
|
|
* each of which comprises:
|
|
* cells 0 - 2: a PCI address
|
|
* cells 3 or 3+4: a CPU physical address
|
|
* (size depending on dev->n_addr_cells)
|
|
* cells 4+5 or 5+6: the size of the range
|
|
*/
|
|
rlen = 0;
|
|
hose->io_base_phys = 0;
|
|
ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
|
|
while ((rlen -= np * sizeof(unsigned int)) >= 0) {
|
|
res = NULL;
|
|
pci_addr = (unsigned long)ranges[1] << 32 | ranges[2];
|
|
|
|
cpu_phys_addr = ranges[3];
|
|
if (na == 2)
|
|
cpu_phys_addr = cpu_phys_addr << 32 | ranges[4];
|
|
|
|
size = (unsigned long)ranges[na+3] << 32 | ranges[na+4];
|
|
if (size == 0)
|
|
continue;
|
|
switch ((ranges[0] >> 24) & 0x3) {
|
|
case 1: /* I/O space */
|
|
hose->io_base_phys = cpu_phys_addr;
|
|
hose->pci_io_size = size;
|
|
|
|
res = &hose->io_resource;
|
|
res->flags = IORESOURCE_IO;
|
|
res->start = pci_addr;
|
|
DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose->global_number,
|
|
res->start, res->start + size - 1);
|
|
break;
|
|
case 2: /* memory space */
|
|
memno = 0;
|
|
while (memno < 3 && hose->mem_resources[memno].flags)
|
|
++memno;
|
|
|
|
if (memno == 0)
|
|
hose->pci_mem_offset = cpu_phys_addr - pci_addr;
|
|
if (memno < 3) {
|
|
res = &hose->mem_resources[memno];
|
|
res->flags = IORESOURCE_MEM;
|
|
res->start = cpu_phys_addr;
|
|
DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose->global_number,
|
|
res->start, res->start + size - 1);
|
|
}
|
|
break;
|
|
}
|
|
if (res != NULL) {
|
|
res->name = dev->full_name;
|
|
res->end = res->start + size - 1;
|
|
res->parent = NULL;
|
|
res->sibling = NULL;
|
|
res->child = NULL;
|
|
}
|
|
ranges += np;
|
|
}
|
|
}
|
|
|
|
void __init pci_setup_phb_io(struct pci_controller *hose, int primary)
|
|
{
|
|
unsigned long size = hose->pci_io_size;
|
|
unsigned long io_virt_offset;
|
|
struct resource *res;
|
|
struct device_node *isa_dn;
|
|
|
|
hose->io_base_virt = reserve_phb_iospace(size);
|
|
DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
|
|
hose->global_number, hose->io_base_phys,
|
|
(unsigned long) hose->io_base_virt);
|
|
|
|
if (primary) {
|
|
pci_io_base = (unsigned long)hose->io_base_virt;
|
|
isa_dn = of_find_node_by_type(NULL, "isa");
|
|
if (isa_dn) {
|
|
isa_io_base = pci_io_base;
|
|
pci_process_ISA_OF_ranges(isa_dn, hose->io_base_phys,
|
|
hose->io_base_virt);
|
|
of_node_put(isa_dn);
|
|
/* Allow all IO */
|
|
io_page_mask = -1;
|
|
}
|
|
}
|
|
|
|
io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
|
|
res = &hose->io_resource;
|
|
res->start += io_virt_offset;
|
|
res->end += io_virt_offset;
|
|
}
|
|
|
|
void __devinit pci_setup_phb_io_dynamic(struct pci_controller *hose,
|
|
int primary)
|
|
{
|
|
unsigned long size = hose->pci_io_size;
|
|
unsigned long io_virt_offset;
|
|
struct resource *res;
|
|
|
|
hose->io_base_virt = __ioremap(hose->io_base_phys, size,
|
|
_PAGE_NO_CACHE | _PAGE_GUARDED);
|
|
DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
|
|
hose->global_number, hose->io_base_phys,
|
|
(unsigned long) hose->io_base_virt);
|
|
|
|
if (primary)
|
|
pci_io_base = (unsigned long)hose->io_base_virt;
|
|
|
|
io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
|
|
res = &hose->io_resource;
|
|
res->start += io_virt_offset;
|
|
res->end += io_virt_offset;
|
|
}
|
|
|
|
|
|
static int get_bus_io_range(struct pci_bus *bus, unsigned long *start_phys,
|
|
unsigned long *start_virt, unsigned long *size)
|
|
{
|
|
struct pci_controller *hose = pci_bus_to_host(bus);
|
|
struct pci_bus_region region;
|
|
struct resource *res;
|
|
|
|
if (bus->self) {
|
|
res = bus->resource[0];
|
|
pcibios_resource_to_bus(bus->self, ®ion, res);
|
|
*start_phys = hose->io_base_phys + region.start;
|
|
*start_virt = (unsigned long) hose->io_base_virt +
|
|
region.start;
|
|
if (region.end > region.start)
|
|
*size = region.end - region.start + 1;
|
|
else {
|
|
printk("%s(): unexpected region 0x%lx->0x%lx\n",
|
|
__FUNCTION__, region.start, region.end);
|
|
return 1;
|
|
}
|
|
|
|
} else {
|
|
/* Root Bus */
|
|
res = &hose->io_resource;
|
|
*start_phys = hose->io_base_phys;
|
|
*start_virt = (unsigned long) hose->io_base_virt;
|
|
if (res->end > res->start)
|
|
*size = res->end - res->start + 1;
|
|
else {
|
|
printk("%s(): unexpected region 0x%lx->0x%lx\n",
|
|
__FUNCTION__, res->start, res->end);
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int unmap_bus_range(struct pci_bus *bus)
|
|
{
|
|
unsigned long start_phys;
|
|
unsigned long start_virt;
|
|
unsigned long size;
|
|
|
|
if (!bus) {
|
|
printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
|
|
return 1;
|
|
}
|
|
|
|
if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
|
|
return 1;
|
|
if (iounmap_explicit((void __iomem *) start_virt, size))
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(unmap_bus_range);
|
|
|
|
int remap_bus_range(struct pci_bus *bus)
|
|
{
|
|
unsigned long start_phys;
|
|
unsigned long start_virt;
|
|
unsigned long size;
|
|
|
|
if (!bus) {
|
|
printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
|
|
return 1;
|
|
}
|
|
|
|
|
|
if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
|
|
return 1;
|
|
printk("mapping IO %lx -> %lx, size: %lx\n", start_phys, start_virt, size);
|
|
if (__ioremap_explicit(start_phys, start_virt, size,
|
|
_PAGE_NO_CACHE | _PAGE_GUARDED))
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(remap_bus_range);
|
|
|
|
void phbs_remap_io(void)
|
|
{
|
|
struct pci_controller *hose, *tmp;
|
|
|
|
list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
|
|
remap_bus_range(hose->bus);
|
|
}
|
|
|
|
/*
|
|
* ppc64 can have multifunction devices that do not respond to function 0.
|
|
* In this case we must scan all functions.
|
|
*/
|
|
int pcibios_scan_all_fns(struct pci_bus *bus, int devfn)
|
|
{
|
|
struct device_node *busdn, *dn;
|
|
|
|
if (bus->self)
|
|
busdn = pci_device_to_OF_node(bus->self);
|
|
else
|
|
busdn = bus->sysdata; /* must be a phb */
|
|
|
|
if (busdn == NULL)
|
|
return 0;
|
|
|
|
/*
|
|
* Check to see if there is any of the 8 functions are in the
|
|
* device tree. If they are then we need to scan all the
|
|
* functions of this slot.
|
|
*/
|
|
for (dn = busdn->child; dn; dn = dn->sibling)
|
|
if ((dn->devfn >> 3) == (devfn >> 3))
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
|
|
struct pci_bus *bus)
|
|
{
|
|
/* Update device resources. */
|
|
struct pci_controller *hose = pci_bus_to_host(bus);
|
|
int i;
|
|
|
|
for (i = 0; i < PCI_NUM_RESOURCES; i++) {
|
|
if (dev->resource[i].flags & IORESOURCE_IO) {
|
|
unsigned long offset = (unsigned long)hose->io_base_virt
|
|
- pci_io_base;
|
|
unsigned long start, end, mask;
|
|
|
|
start = dev->resource[i].start += offset;
|
|
end = dev->resource[i].end += offset;
|
|
|
|
/* Need to allow IO access to pages that are in the
|
|
ISA range */
|
|
if (start < MAX_ISA_PORT) {
|
|
if (end > MAX_ISA_PORT)
|
|
end = MAX_ISA_PORT;
|
|
|
|
start >>= PAGE_SHIFT;
|
|
end >>= PAGE_SHIFT;
|
|
|
|
/* get the range of pages for the map */
|
|
mask = ((1 << (end+1))-1) ^ ((1 << start)-1);
|
|
io_page_mask |= mask;
|
|
}
|
|
}
|
|
else if (dev->resource[i].flags & IORESOURCE_MEM) {
|
|
dev->resource[i].start += hose->pci_mem_offset;
|
|
dev->resource[i].end += hose->pci_mem_offset;
|
|
}
|
|
}
|
|
}
|
|
EXPORT_SYMBOL(pcibios_fixup_device_resources);
|
|
|
|
void __devinit pcibios_fixup_bus(struct pci_bus *bus)
|
|
{
|
|
struct pci_controller *hose = pci_bus_to_host(bus);
|
|
struct pci_dev *dev = bus->self;
|
|
struct resource *res;
|
|
int i;
|
|
|
|
if (!dev) {
|
|
/* Root bus. */
|
|
|
|
hose->bus = bus;
|
|
bus->resource[0] = res = &hose->io_resource;
|
|
|
|
if (res->flags && request_resource(&ioport_resource, res))
|
|
printk(KERN_ERR "Failed to request IO on "
|
|
"PCI domain %d\n", pci_domain_nr(bus));
|
|
|
|
for (i = 0; i < 3; ++i) {
|
|
res = &hose->mem_resources[i];
|
|
bus->resource[i+1] = res;
|
|
if (res->flags && request_resource(&iomem_resource, res))
|
|
printk(KERN_ERR "Failed to request MEM on "
|
|
"PCI domain %d\n",
|
|
pci_domain_nr(bus));
|
|
}
|
|
} else if (pci_probe_only &&
|
|
(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
|
|
/* This is a subordinate bridge */
|
|
|
|
pci_read_bridge_bases(bus);
|
|
pcibios_fixup_device_resources(dev, bus);
|
|
}
|
|
|
|
ppc_md.iommu_bus_setup(bus);
|
|
|
|
list_for_each_entry(dev, &bus->devices, bus_list)
|
|
ppc_md.iommu_dev_setup(dev);
|
|
|
|
if (ppc_md.irq_bus_setup)
|
|
ppc_md.irq_bus_setup(bus);
|
|
|
|
if (!pci_probe_only)
|
|
return;
|
|
|
|
list_for_each_entry(dev, &bus->devices, bus_list) {
|
|
if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
|
|
pcibios_fixup_device_resources(dev, bus);
|
|
}
|
|
}
|
|
EXPORT_SYMBOL(pcibios_fixup_bus);
|
|
|
|
/*
|
|
* Reads the interrupt pin to determine if interrupt is use by card.
|
|
* If the interrupt is used, then gets the interrupt line from the
|
|
* openfirmware and sets it in the pci_dev and pci_config line.
|
|
*/
|
|
int pci_read_irq_line(struct pci_dev *pci_dev)
|
|
{
|
|
u8 intpin;
|
|
struct device_node *node;
|
|
|
|
pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &intpin);
|
|
if (intpin == 0)
|
|
return 0;
|
|
|
|
node = pci_device_to_OF_node(pci_dev);
|
|
if (node == NULL)
|
|
return -1;
|
|
|
|
if (node->n_intrs == 0)
|
|
return -1;
|
|
|
|
pci_dev->irq = node->intrs[0].line;
|
|
|
|
pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, pci_dev->irq);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(pci_read_irq_line);
|
|
|
|
void pci_resource_to_user(const struct pci_dev *dev, int bar,
|
|
const struct resource *rsrc,
|
|
u64 *start, u64 *end)
|
|
{
|
|
struct pci_controller *hose = pci_bus_to_host(dev->bus);
|
|
unsigned long offset = 0;
|
|
|
|
if (hose == NULL)
|
|
return;
|
|
|
|
if (rsrc->flags & IORESOURCE_IO)
|
|
offset = pci_io_base - (unsigned long)hose->io_base_virt +
|
|
hose->io_base_phys;
|
|
|
|
*start = rsrc->start + offset;
|
|
*end = rsrc->end + offset;
|
|
}
|
|
|
|
#endif /* CONFIG_PPC_MULTIPLATFORM */
|