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6973f0a0c7
This patch add RNG instance of the stm32mp157c SoC Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
662 lines
14 KiB
Plaintext
662 lines
14 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
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* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/stm32mp1-clks.h>
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#include <dt-bindings/reset/stm32mp1-resets.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <1>;
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};
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};
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psci {
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compatible = "arm,psci";
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method = "smc";
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cpu_off = <0x84000002>;
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cpu_on = <0x84000003>;
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};
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aliases {
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gpio0 = &gpioa;
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gpio1 = &gpiob;
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gpio2 = &gpioc;
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gpio3 = &gpiod;
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gpio4 = &gpioe;
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gpio5 = &gpiof;
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gpio6 = &gpiog;
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gpio7 = &gpioh;
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gpio8 = &gpioi;
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gpio9 = &gpioj;
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gpio10 = &gpiok;
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};
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intc: interrupt-controller@a0021000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xa0021000 0x1000>,
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<0xa0022000 0x2000>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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interrupt-parent = <&intc>;
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};
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <64000000>;
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};
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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};
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clk_csi: clk-csi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <4000000>;
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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ranges;
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timers2: timer@40000000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40000000 0x400>;
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clocks = <&rcc TIM2_K>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@1 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <1>;
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status = "disabled";
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};
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};
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timers3: timer@40001000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40001000 0x400>;
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clocks = <&rcc TIM3_K>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@2 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <2>;
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status = "disabled";
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};
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};
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timers4: timer@40002000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40002000 0x400>;
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clocks = <&rcc TIM4_K>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@3 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <3>;
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status = "disabled";
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};
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};
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timers5: timer@40003000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40003000 0x400>;
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clocks = <&rcc TIM5_K>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@4 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <4>;
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status = "disabled";
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};
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};
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timers6: timer@40004000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40004000 0x400>;
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clocks = <&rcc TIM6_K>;
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clock-names = "int";
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status = "disabled";
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timer@5 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <5>;
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status = "disabled";
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};
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};
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timers7: timer@40005000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40005000 0x400>;
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clocks = <&rcc TIM7_K>;
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clock-names = "int";
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status = "disabled";
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timer@6 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <6>;
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status = "disabled";
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};
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};
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timers12: timer@40006000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40006000 0x400>;
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clocks = <&rcc TIM12_K>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@11 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <11>;
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status = "disabled";
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};
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};
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timers13: timer@40007000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40007000 0x400>;
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clocks = <&rcc TIM13_K>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@12 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <12>;
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status = "disabled";
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};
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};
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timers14: timer@40008000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40008000 0x400>;
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clocks = <&rcc TIM14_K>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@13 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <13>;
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status = "disabled";
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};
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};
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lptimer1: timer@40009000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-lptimer";
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reg = <0x40009000 0x400>;
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clocks = <&rcc LPTIM1_K>;
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clock-names = "mux";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm-lp";
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#pwm-cells = <3>;
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status = "disabled";
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};
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trigger@0 {
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compatible = "st,stm32-lptimer-trigger";
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reg = <0>;
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status = "disabled";
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};
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counter {
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compatible = "st,stm32-lptimer-counter";
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status = "disabled";
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};
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};
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usart2: serial@4000e000 {
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compatible = "st,stm32h7-uart";
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reg = <0x4000e000 0x400>;
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interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>;
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clocks = <&rcc USART2_K>;
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status = "disabled";
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};
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usart3: serial@4000f000 {
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compatible = "st,stm32h7-uart";
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reg = <0x4000f000 0x400>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_NONE>;
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clocks = <&rcc USART3_K>;
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status = "disabled";
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};
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uart4: serial@40010000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40010000 0x400>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_NONE>;
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clocks = <&rcc UART4_K>;
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status = "disabled";
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};
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uart5: serial@40011000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40011000 0x400>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;
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clocks = <&rcc UART5_K>;
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status = "disabled";
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};
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dac: dac@40017000 {
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compatible = "st,stm32h7-dac-core";
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reg = <0x40017000 0x400>;
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clocks = <&rcc DAC12>;
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clock-names = "pclk";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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dac1: dac@1 {
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compatible = "st,stm32-dac";
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#io-channels-cells = <1>;
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reg = <1>;
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status = "disabled";
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};
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dac2: dac@2 {
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compatible = "st,stm32-dac";
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#io-channels-cells = <1>;
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reg = <2>;
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status = "disabled";
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};
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};
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uart7: serial@40018000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40018000 0x400>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_NONE>;
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clocks = <&rcc UART7_K>;
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status = "disabled";
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};
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uart8: serial@40019000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40019000 0x400>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_NONE>;
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clocks = <&rcc UART8_K>;
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status = "disabled";
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};
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timers1: timer@44000000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x44000000 0x400>;
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clocks = <&rcc TIM1_K>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@0 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <0>;
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status = "disabled";
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};
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};
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timers8: timer@44001000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x44001000 0x400>;
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clocks = <&rcc TIM8_K>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@7 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <7>;
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status = "disabled";
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};
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};
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usart6: serial@44003000 {
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compatible = "st,stm32h7-uart";
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reg = <0x44003000 0x400>;
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interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
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clocks = <&rcc USART6_K>;
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status = "disabled";
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};
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timers15: timer@44006000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x44006000 0x400>;
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clocks = <&rcc TIM15_K>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@14 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <14>;
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status = "disabled";
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};
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};
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timers16: timer@44007000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x44007000 0x400>;
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clocks = <&rcc TIM16_K>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@15 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <15>;
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status = "disabled";
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};
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};
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timers17: timer@44008000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x44008000 0x400>;
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clocks = <&rcc TIM17_K>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@16 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <16>;
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status = "disabled";
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};
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};
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dma1: dma@48000000 {
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compatible = "st,stm32-dma";
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reg = <0x48000000 0x400>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc DMA1>;
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#dma-cells = <4>;
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st,mem2mem;
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dma-requests = <8>;
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};
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dma2: dma@48001000 {
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compatible = "st,stm32-dma";
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reg = <0x48001000 0x400>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc DMA2>;
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#dma-cells = <4>;
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st,mem2mem;
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dma-requests = <8>;
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};
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dmamux1: dma-router@48002000 {
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compatible = "st,stm32h7-dmamux";
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reg = <0x48002000 0x1c>;
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#dma-cells = <3>;
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dma-requests = <128>;
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dma-masters = <&dma1 &dma2>;
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dma-channels = <16>;
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clocks = <&rcc DMAMUX>;
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};
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rcc: rcc@50000000 {
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compatible = "st,stm32mp1-rcc", "syscon";
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reg = <0x50000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
|
|
};
|
|
|
|
lptimer2: timer@50021000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-lptimer";
|
|
reg = <0x50021000 0x400>;
|
|
clocks = <&rcc LPTIM2_K>;
|
|
clock-names = "mux";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm-lp";
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
trigger@1 {
|
|
compatible = "st,stm32-lptimer-trigger";
|
|
reg = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
counter {
|
|
compatible = "st,stm32-lptimer-counter";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
lptimer3: timer@50022000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-lptimer";
|
|
reg = <0x50022000 0x400>;
|
|
clocks = <&rcc LPTIM3_K>;
|
|
clock-names = "mux";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm-lp";
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
trigger@2 {
|
|
compatible = "st,stm32-lptimer-trigger";
|
|
reg = <2>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
lptimer4: timer@50023000 {
|
|
compatible = "st,stm32-lptimer";
|
|
reg = <0x50023000 0x400>;
|
|
clocks = <&rcc LPTIM4_K>;
|
|
clock-names = "mux";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm-lp";
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
lptimer5: timer@50024000 {
|
|
compatible = "st,stm32-lptimer";
|
|
reg = <0x50024000 0x400>;
|
|
clocks = <&rcc LPTIM5_K>;
|
|
clock-names = "mux";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm-lp";
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
vrefbuf: vrefbuf@50025000 {
|
|
compatible = "st,stm32-vrefbuf";
|
|
reg = <0x50025000 0x8>;
|
|
regulator-min-microvolt = <1500000>;
|
|
regulator-max-microvolt = <2500000>;
|
|
clocks = <&rcc VREF>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rng1: rng@54003000 {
|
|
compatible = "st,stm32-rng";
|
|
reg = <0x54003000 0x400>;
|
|
clocks = <&rcc RNG1_K>;
|
|
resets = <&rcc RNG1_R>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mdma1: dma@58000000 {
|
|
compatible = "st,stm32h7-mdma";
|
|
reg = <0x58000000 0x1000>;
|
|
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&rcc MDMA>;
|
|
#dma-cells = <5>;
|
|
dma-channels = <32>;
|
|
dma-requests = <48>;
|
|
};
|
|
|
|
usart1: serial@5c000000 {
|
|
compatible = "st,stm32h7-uart";
|
|
reg = <0x5c000000 0x400>;
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_NONE>;
|
|
clocks = <&rcc USART1_K>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|