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Document the introduction and usage of HiSilicon PTT device driver as well as the sysfs attributes description provided by the driver. Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Bagas Sanjaya <bagasdotme@gmail.com> [Fixed month and kernel version] Link: https://lore.kernel.org/r/20220816114414.4092-5-yangyicong@huawei.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
62 lines
2.8 KiB
Plaintext
62 lines
2.8 KiB
Plaintext
What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/tune
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Date: October 2022
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KernelVersion: 6.1
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Contact: Yicong Yang <yangyicong@hisilicon.com>
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Description: This directory contains files for tuning the PCIe link
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parameters(events). Each file is named after the event
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of the PCIe link.
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See Documentation/trace/hisi-ptt.rst for more information.
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What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/tune/qos_tx_cpl
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Date: October 2022
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KernelVersion: 6.1
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Contact: Yicong Yang <yangyicong@hisilicon.com>
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Description: (RW) Controls the weight of Tx completion TLPs, which influence
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the proportion of outbound completion TLPs on the PCIe link.
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The available tune data is [0, 1, 2]. Writing a negative value
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will return an error, and out of range values will be converted
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to 2. The value indicates a probable level of the event.
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What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/tune/qos_tx_np
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Date: October 2022
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KernelVersion: 6.1
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Contact: Yicong Yang <yangyicong@hisilicon.com>
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Description: (RW) Controls the weight of Tx non-posted TLPs, which influence
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the proportion of outbound non-posted TLPs on the PCIe link.
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The available tune data is [0, 1, 2]. Writing a negative value
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will return an error, and out of range values will be converted
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to 2. The value indicates a probable level of the event.
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What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/tune/qos_tx_p
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Date: October 2022
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KernelVersion: 6.1
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Contact: Yicong Yang <yangyicong@hisilicon.com>
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Description: (RW) Controls the weight of Tx posted TLPs, which influence the
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proportion of outbound posted TLPs on the PCIe link.
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The available tune data is [0, 1, 2]. Writing a negative value
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will return an error, and out of range values will be converted
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to 2. The value indicates a probable level of the event.
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What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/tune/rx_alloc_buf_level
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Date: October 2022
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KernelVersion: 6.1
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Contact: Yicong Yang <yangyicong@hisilicon.com>
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Description: (RW) Control the allocated buffer watermark for inbound packets.
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The packets will be stored in the buffer first and then transmitted
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either when the watermark reached or when timed out.
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The available tune data is [0, 1, 2]. Writing a negative value
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will return an error, and out of range values will be converted
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to 2. The value indicates a probable level of the event.
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What: /sys/devices/hisi_ptt<sicl_id>_<core_id>/tune/tx_alloc_buf_level
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Date: October 2022
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KernelVersion: 6.1
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Contact: Yicong Yang <yangyicong@hisilicon.com>
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Description: (RW) Control the allocated buffer watermark of outbound packets.
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The packets will be stored in the buffer first and then transmitted
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either when the watermark reached or when timed out.
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The available tune data is [0, 1, 2]. Writing a negative value
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will return an error, and out of range values will be converted
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to 2. The value indicates a probable level of the event.
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