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a9e192cd4f
commit 11663111cd
("KVM: arm64: Hide PMU registers from userspace when
not available") hid the AArch64 PMU registers from userspace and guest
when the PMU VCPU feature was not set. Do the same when the PMU
registers are accessed by an AArch32 guest. While we're at it, rename
the previously unused AA32_ZEROHIGH to AA32_DIRECT to match the behavior
of get_access_mask().
Now that KVM emulates ID_DFR0 and hides the PMU from the guest when the
feature is not set, it is safe to inject to inject an undefined exception
when the PMU is not present, as that corresponds to the architected
behaviour.
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
[Oliver - Add AA32_DIRECT to match the zero value of the enum]
Signed-off-by: Oliver Upton <oupton@google.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220503060205.2823727-7-oupton@google.com
212 lines
5.4 KiB
C
212 lines
5.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* Derived from arch/arm/kvm/coproc.h
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Authors: Christoffer Dall <c.dall@virtualopensystems.com>
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*/
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#ifndef __ARM64_KVM_SYS_REGS_LOCAL_H__
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#define __ARM64_KVM_SYS_REGS_LOCAL_H__
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#include <linux/bsearch.h>
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#define reg_to_encoding(x) \
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sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \
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(u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2)
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struct sys_reg_params {
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u8 Op0;
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u8 Op1;
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u8 CRn;
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u8 CRm;
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u8 Op2;
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u64 regval;
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bool is_write;
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};
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#define esr_sys64_to_params(esr) \
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((struct sys_reg_params){ .Op0 = ((esr) >> 20) & 3, \
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.Op1 = ((esr) >> 14) & 0x7, \
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.CRn = ((esr) >> 10) & 0xf, \
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.CRm = ((esr) >> 1) & 0xf, \
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.Op2 = ((esr) >> 17) & 0x7, \
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.is_write = !((esr) & 1) })
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#define esr_cp1x_32_to_params(esr) \
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((struct sys_reg_params){ .Op1 = ((esr) >> 14) & 0x7, \
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.CRn = ((esr) >> 10) & 0xf, \
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.CRm = ((esr) >> 1) & 0xf, \
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.Op2 = ((esr) >> 17) & 0x7, \
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.is_write = !((esr) & 1) })
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struct sys_reg_desc {
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/* Sysreg string for debug */
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const char *name;
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enum {
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AA32_DIRECT,
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AA32_LO,
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AA32_HI,
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} aarch32_map;
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/* MRS/MSR instruction which accesses it. */
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u8 Op0;
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u8 Op1;
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u8 CRn;
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u8 CRm;
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u8 Op2;
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/* Trapped access from guest, if non-NULL. */
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bool (*access)(struct kvm_vcpu *,
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struct sys_reg_params *,
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const struct sys_reg_desc *);
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/* Initialization for vcpu. */
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void (*reset)(struct kvm_vcpu *, const struct sys_reg_desc *);
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/* Index into sys_reg[], or 0 if we don't need to save it. */
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int reg;
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/* Value (usually reset value) */
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u64 val;
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/* Custom get/set_user functions, fallback to generic if NULL */
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int (*get_user)(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
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const struct kvm_one_reg *reg, void __user *uaddr);
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int (*set_user)(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
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const struct kvm_one_reg *reg, void __user *uaddr);
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/* Return mask of REG_* runtime visibility overrides */
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unsigned int (*visibility)(const struct kvm_vcpu *vcpu,
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const struct sys_reg_desc *rd);
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};
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#define REG_HIDDEN (1 << 0) /* hidden from userspace and guest */
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#define REG_RAZ (1 << 1) /* RAZ from userspace and guest */
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static __printf(2, 3)
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inline void print_sys_reg_msg(const struct sys_reg_params *p,
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char *fmt, ...)
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{
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va_list va;
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va_start(va, fmt);
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/* Look, we even formatted it for you to paste into the table! */
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kvm_pr_unimpl("%pV { Op0(%2u), Op1(%2u), CRn(%2u), CRm(%2u), Op2(%2u), func_%s },\n",
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&(struct va_format){ fmt, &va },
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p->Op0, p->Op1, p->CRn, p->CRm, p->Op2, p->is_write ? "write" : "read");
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va_end(va);
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}
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static inline void print_sys_reg_instr(const struct sys_reg_params *p)
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{
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/* GCC warns on an empty format string */
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print_sys_reg_msg(p, "%s", "");
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}
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static inline bool ignore_write(struct kvm_vcpu *vcpu,
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const struct sys_reg_params *p)
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{
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return true;
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}
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static inline bool read_zero(struct kvm_vcpu *vcpu,
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struct sys_reg_params *p)
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{
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p->regval = 0;
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return true;
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}
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/* Reset functions */
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static inline void reset_unknown(struct kvm_vcpu *vcpu,
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const struct sys_reg_desc *r)
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{
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BUG_ON(!r->reg);
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BUG_ON(r->reg >= NR_SYS_REGS);
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__vcpu_sys_reg(vcpu, r->reg) = 0x1de7ec7edbadc0deULL;
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}
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static inline void reset_val(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
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{
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BUG_ON(!r->reg);
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BUG_ON(r->reg >= NR_SYS_REGS);
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__vcpu_sys_reg(vcpu, r->reg) = r->val;
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}
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static inline bool sysreg_hidden(const struct kvm_vcpu *vcpu,
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const struct sys_reg_desc *r)
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{
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if (likely(!r->visibility))
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return false;
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return r->visibility(vcpu, r) & REG_HIDDEN;
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}
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static inline bool sysreg_visible_as_raz(const struct kvm_vcpu *vcpu,
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const struct sys_reg_desc *r)
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{
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if (likely(!r->visibility))
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return false;
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return r->visibility(vcpu, r) & REG_RAZ;
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}
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static inline int cmp_sys_reg(const struct sys_reg_desc *i1,
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const struct sys_reg_desc *i2)
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{
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BUG_ON(i1 == i2);
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if (!i1)
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return 1;
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else if (!i2)
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return -1;
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if (i1->Op0 != i2->Op0)
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return i1->Op0 - i2->Op0;
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if (i1->Op1 != i2->Op1)
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return i1->Op1 - i2->Op1;
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if (i1->CRn != i2->CRn)
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return i1->CRn - i2->CRn;
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if (i1->CRm != i2->CRm)
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return i1->CRm - i2->CRm;
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return i1->Op2 - i2->Op2;
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}
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static inline int match_sys_reg(const void *key, const void *elt)
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{
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const unsigned long pval = (unsigned long)key;
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const struct sys_reg_desc *r = elt;
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return pval - reg_to_encoding(r);
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}
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static inline const struct sys_reg_desc *
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find_reg(const struct sys_reg_params *params, const struct sys_reg_desc table[],
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unsigned int num)
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{
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unsigned long pval = reg_to_encoding(params);
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return __inline_bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
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}
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const struct sys_reg_desc *find_reg_by_id(u64 id,
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struct sys_reg_params *params,
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const struct sys_reg_desc table[],
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unsigned int num);
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#define AA32(_x) .aarch32_map = AA32_##_x
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#define Op0(_x) .Op0 = _x
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#define Op1(_x) .Op1 = _x
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#define CRn(_x) .CRn = _x
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#define CRm(_x) .CRm = _x
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#define Op2(_x) .Op2 = _x
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#define SYS_DESC(reg) \
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.name = #reg, \
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Op0(sys_reg_Op0(reg)), Op1(sys_reg_Op1(reg)), \
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CRn(sys_reg_CRn(reg)), CRm(sys_reg_CRm(reg)), \
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Op2(sys_reg_Op2(reg))
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#endif /* __ARM64_KVM_SYS_REGS_LOCAL_H__ */
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