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Apple SoCs (A11 and newer) have some interrupt sources hardwired to the FIQ line. We implement support for this by simply treating IRQs and FIQs the same way in the interrupt vectors. To support these systems, the FIQ mask bit needs to be kept in sync with the IRQ mask bit, so both kinds of exceptions are masked together. No other platforms should be delivering FIQ exceptions right now, and we already unmask FIQ in normal process context, so this should not have an effect on other systems - if spurious FIQs were arriving, they would already panic the kernel. Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Tested-by: Hector Martin <marcan@marcan.st> Cc: James Morse <james.morse@arm.com> Cc: Marc Zyngier <maz@kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Will Deacon <will@kernel.org> Acked-by: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20210315115629.57191-6-mark.rutland@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
134 lines
2.9 KiB
C
134 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __ASM_IRQFLAGS_H
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#define __ASM_IRQFLAGS_H
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#include <asm/alternative.h>
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#include <asm/barrier.h>
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#include <asm/ptrace.h>
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#include <asm/sysreg.h>
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/*
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* Aarch64 has flags for masking: Debug, Asynchronous (serror), Interrupts and
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* FIQ exceptions, in the 'daif' register. We mask and unmask them in 'daif'
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* order:
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* Masking debug exceptions causes all other exceptions to be masked too/
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* Masking SError masks IRQ/FIQ, but not debug exceptions. IRQ and FIQ are
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* always masked and unmasked together, and have no side effects for other
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* flags. Keeping to this order makes it easier for entry.S to know which
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* exceptions should be unmasked.
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*/
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/*
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* CPU interrupt mask handling.
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*/
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static inline void arch_local_irq_enable(void)
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{
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if (system_has_prio_mask_debugging()) {
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u32 pmr = read_sysreg_s(SYS_ICC_PMR_EL1);
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WARN_ON_ONCE(pmr != GIC_PRIO_IRQON && pmr != GIC_PRIO_IRQOFF);
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}
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asm volatile(ALTERNATIVE(
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"msr daifclr, #3 // arch_local_irq_enable",
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__msr_s(SYS_ICC_PMR_EL1, "%0"),
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ARM64_HAS_IRQ_PRIO_MASKING)
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:
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: "r" ((unsigned long) GIC_PRIO_IRQON)
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: "memory");
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pmr_sync();
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}
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static inline void arch_local_irq_disable(void)
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{
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if (system_has_prio_mask_debugging()) {
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u32 pmr = read_sysreg_s(SYS_ICC_PMR_EL1);
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WARN_ON_ONCE(pmr != GIC_PRIO_IRQON && pmr != GIC_PRIO_IRQOFF);
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}
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asm volatile(ALTERNATIVE(
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"msr daifset, #3 // arch_local_irq_disable",
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__msr_s(SYS_ICC_PMR_EL1, "%0"),
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ARM64_HAS_IRQ_PRIO_MASKING)
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:
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: "r" ((unsigned long) GIC_PRIO_IRQOFF)
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: "memory");
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}
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/*
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* Save the current interrupt enable state.
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*/
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static inline unsigned long arch_local_save_flags(void)
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{
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unsigned long flags;
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asm volatile(ALTERNATIVE(
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"mrs %0, daif",
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__mrs_s("%0", SYS_ICC_PMR_EL1),
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ARM64_HAS_IRQ_PRIO_MASKING)
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: "=&r" (flags)
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:
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: "memory");
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return flags;
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}
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static inline int arch_irqs_disabled_flags(unsigned long flags)
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{
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int res;
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asm volatile(ALTERNATIVE(
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"and %w0, %w1, #" __stringify(PSR_I_BIT),
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"eor %w0, %w1, #" __stringify(GIC_PRIO_IRQON),
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ARM64_HAS_IRQ_PRIO_MASKING)
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: "=&r" (res)
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: "r" ((int) flags)
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: "memory");
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return res;
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}
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static inline int arch_irqs_disabled(void)
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{
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return arch_irqs_disabled_flags(arch_local_save_flags());
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}
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static inline unsigned long arch_local_irq_save(void)
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{
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unsigned long flags;
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flags = arch_local_save_flags();
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/*
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* There are too many states with IRQs disabled, just keep the current
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* state if interrupts are already disabled/masked.
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*/
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if (!arch_irqs_disabled_flags(flags))
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arch_local_irq_disable();
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return flags;
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}
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/*
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* restore saved IRQ state
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*/
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static inline void arch_local_irq_restore(unsigned long flags)
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{
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asm volatile(ALTERNATIVE(
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"msr daif, %0",
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__msr_s(SYS_ICC_PMR_EL1, "%0"),
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ARM64_HAS_IRQ_PRIO_MASKING)
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:
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: "r" (flags)
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: "memory");
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pmr_sync();
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}
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#endif /* __ASM_IRQFLAGS_H */
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