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The Low-Power Mode, when enabled, will make the "wait" MIPS instruction suspend the system. This is not really clock-related, but this bit happens to be in the register set of the CGU. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
46 lines
999 B
C
46 lines
999 B
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Paul Cercueil <paul@crapouillou.net>
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*/
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#include "cgu.h"
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#include "pm.h"
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#include <linux/io.h>
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#include <linux/syscore_ops.h>
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#define CGU_REG_LCR 0x04
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#define LCR_LOW_POWER_MODE BIT(0)
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static void __iomem * __maybe_unused ingenic_cgu_base;
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static int __maybe_unused ingenic_cgu_pm_suspend(void)
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{
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u32 val = readl(ingenic_cgu_base + CGU_REG_LCR);
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writel(val | LCR_LOW_POWER_MODE, ingenic_cgu_base + CGU_REG_LCR);
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return 0;
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}
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static void __maybe_unused ingenic_cgu_pm_resume(void)
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{
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u32 val = readl(ingenic_cgu_base + CGU_REG_LCR);
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writel(val & ~LCR_LOW_POWER_MODE, ingenic_cgu_base + CGU_REG_LCR);
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}
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static struct syscore_ops __maybe_unused ingenic_cgu_pm_ops = {
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.suspend = ingenic_cgu_pm_suspend,
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.resume = ingenic_cgu_pm_resume,
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};
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void ingenic_cgu_register_syscore_ops(struct ingenic_cgu *cgu)
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{
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if (IS_ENABLED(CONFIG_PM_SLEEP)) {
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ingenic_cgu_base = cgu->base;
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register_syscore_ops(&ingenic_cgu_pm_ops);
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}
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}
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