mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-17 07:54:54 +08:00
68ddbf09ec
KVM would like to consume any pending SError (or RAS error) after guest exit. Today it has to unmask SError and use dsb+isb to synchronise the CPU. With the RAS extensions we can use ESB to synchronise any pending SError. Add the necessary macros to allow DISR to be read and converted to an ESR. We clear the DISR register when we enable the RAS cpufeature, and the kernel has not executed any ESB instructions. Any value we find in DISR must have belonged to firmware. Executing an ESB instruction is the only way to update DISR, so we can expect firmware to have handled any deferred SError. By the same logic we clear DISR in the idle path. Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: James Morse <james.morse@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
45 lines
1.2 KiB
C
45 lines
1.2 KiB
C
/*
|
|
* Based on arch/arm/include/asm/exception.h
|
|
*
|
|
* Copyright (C) 2012 ARM Ltd.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
#ifndef __ASM_EXCEPTION_H
|
|
#define __ASM_EXCEPTION_H
|
|
|
|
#include <asm/esr.h>
|
|
|
|
#include <linux/interrupt.h>
|
|
|
|
#define __exception __attribute__((section(".exception.text")))
|
|
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
|
|
#define __exception_irq_entry __irq_entry
|
|
#else
|
|
#define __exception_irq_entry __exception
|
|
#endif
|
|
|
|
static inline u32 disr_to_esr(u64 disr)
|
|
{
|
|
unsigned int esr = ESR_ELx_EC_SERROR << ESR_ELx_EC_SHIFT;
|
|
|
|
if ((disr & DISR_EL1_IDS) == 0)
|
|
esr |= (disr & DISR_EL1_ESR_MASK);
|
|
else
|
|
esr |= (disr & ESR_ELx_ISS_MASK);
|
|
|
|
return esr;
|
|
}
|
|
|
|
#endif /* __ASM_EXCEPTION_H */
|