linux/drivers/clk/rockchip
Chris Morgan 685da69726 clk: rockchip: rk3568: Add PLL rate for 126.4MHz
Add support for a PLL rate of 126.4MHz so that the Powkiddy X55 panel
can run at a requested 60hz.

I have confirmed this rate fits with all the constraints
listed in the TRM for the VPLL (as an integer PLL) in Part 1 "Chapter
2 Clock & Reset Unit (CRU)."

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Link: https://lore.kernel.org/r/20231204185719.569021-9-macroalpha82@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-12-05 10:43:42 +01:00
..
clk-cpu.c clk: rockchip: allow additional mux options for cpu-clock frequency changes 2022-11-14 15:34:18 +01:00
clk-ddr.c clk: rockchip: Export rockchip_clk_register_ddrclk() 2020-09-22 15:16:37 +02:00
clk-half-divider.c clk: rockchip: Demote non-conformant kernel-doc header in half-divider 2021-01-26 00:24:05 +01:00
clk-inverter.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 2019-05-30 11:26:37 -07:00
clk-mmc-phase.c clk: rockchip: fix mmc get phase 2020-03-06 12:06:01 -08:00
clk-muxgrf.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282 2019-06-05 17:36:37 +02:00
clk-pll.c clk: rockchip: Fix memory leak in rockchip_clk_register_pll() 2022-11-23 14:51:30 +01:00
clk-px30.c clk: rockchip: support more core div setting 2021-03-21 11:10:58 +01:00
clk-rk3036.c clk: rockchip: Add support for hclk_sfc on rk3036 2021-07-16 00:33:42 +02:00
clk-rk3128.c clk: rockchip: support more core div setting 2021-03-21 11:10:58 +01:00
clk-rk3188.c clk: rockchip: support more core div setting 2021-03-21 11:10:58 +01:00
clk-rk3228.c clk: rockchip: support more core div setting 2021-03-21 11:10:58 +01:00
clk-rk3288.c clk: rockchip: support more core div setting 2021-03-21 11:10:58 +01:00
clk-rk3308.c clk: rockchip: make rk3308 ddrphy4x clock critical 2021-07-29 12:43:11 +02:00
clk-rk3328.c clk: rockchip: support more core div setting 2021-03-21 11:10:58 +01:00
clk-rk3368.c clk: rockchip: support more core div setting 2021-03-21 11:10:58 +01:00
clk-rk3399.c clk: Use device_get_match_data() 2023-10-23 20:16:21 -07:00
clk-rk3568.c clk: rockchip: rk3568: Add PLL rate for 126.4MHz 2023-12-05 10:43:42 +01:00
clk-rk3588.c clk: rockchip: rk3588: make gate linked clocks critical 2023-04-18 00:54:04 +02:00
clk-rv1108.c clk: rockchip: support more core div setting 2021-03-21 11:10:58 +01:00
clk-rv1126.c Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and 'clk-rockchip' into clk-next 2023-08-30 14:38:19 -07:00
clk.c clk: rockchip: Remove values for mmask and nmask in struct clk_fractional_divider 2023-04-05 12:09:27 -07:00
clk.h clk: rockchip: add clock controller for the RK3588 2022-11-15 11:37:41 +01:00
Kconfig clk: rockchip: add clock controller for the RK3588 2022-11-15 11:37:41 +01:00
Makefile clk: rockchip: add clock controller for the RK3588 2022-11-15 11:37:41 +01:00
rst-rk3588.c clk: rockchip: add clock controller for the RK3588 2022-11-15 11:37:41 +01:00
softrst.c clk: rockchip: add lookup table support 2022-11-14 15:35:07 +01:00