linux/drivers/clk/socfpga
Dinh Nguyen 6855ee8396 clk: agilex/stratix10: fix bypass representation
Each of these clocks(s2f_usr0/1, sdmmc_clk, gpio_db, emac_ptp,
emac0/1/2) have a bypass setting that can use the boot_clk. The
previous representation was not correct.

Fix the representation.

Fixes: 80c6b7a089 ("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc: stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210611025201.118799-2-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27 16:39:59 -07:00
..
clk-agilex.c clk: agilex/stratix10: fix bypass representation 2021-06-27 16:39:59 -07:00
clk-gate-a10.c clk: socfpga: arria10: Fix memory leak of socfpga_clk on error return 2021-04-07 16:29:31 -07:00
clk-gate-s10.c clk: socfpga: remove redundant initialization of variable div 2021-04-07 16:30:23 -07:00
clk-gate.c Merge branches 'clk-cleanup', 'clk-renesas', 'clk-socfpga', 'clk-allwinner' and 'clk-qcom' into clk-next 2021-04-27 16:34:28 -07:00
clk-periph-a10.c clk: socfpga: arria10: convert to use clk_hw 2021-03-30 19:26:26 -07:00
clk-periph-s10.c clk: socfpga: Convert to s10/agilex/n5x to use clk_hw 2021-03-30 19:26:26 -07:00
clk-periph.c clk: socfpga: use clk_hw_register for a5/c5 2021-03-30 19:26:26 -07:00
clk-pll-a10.c clk: socfpga: arria10: convert to use clk_hw 2021-03-30 19:26:26 -07:00
clk-pll-s10.c clk: socfpga: remove redundant initialization of variable div 2021-04-07 16:30:23 -07:00
clk-pll.c clk: socfpga: use clk_hw_register for a5/c5 2021-03-30 19:26:26 -07:00
clk-s10.c clk: agilex/stratix10: fix bypass representation 2021-06-27 16:39:59 -07:00
clk.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13 2019-05-21 11:28:45 +02:00
clk.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288 2019-06-05 17:36:37 +02:00
Kconfig clk: socfpga: use ARCH_INTEL_SOCFPGA also for 32-bit ARM SoCs (and compile test) 2021-03-23 11:03:36 -05:00
Makefile clk: socfpga: use ARCH_INTEL_SOCFPGA also for 32-bit ARM SoCs (and compile test) 2021-03-23 11:03:36 -05:00
stratix10-clk.h clk: socfpga: Convert to s10/agilex/n5x to use clk_hw 2021-03-30 19:26:26 -07:00