Imre Deak 67fba3f1c7 drm/i915/dp: Fix LTTPR vswing/pre-emp setting in non-transparent mode ... The DP PHY vswing/pre-emphasis level programming the driver does is related to the DPTX -> first LTTPR link segment only. Accordingly it should be only programmed when link training the first LTTPR and kept as-is when training subsequent LTTPRs and the DPRX. For these latter PHYs the vs/pe levels will be set in response to writing the DP_TRAINING_LANEx_SET_PHY_REPEATERy DPCD registers (by an upstream LTTPR TX PHY snooping this write access of its downstream LTTPR/DPRX RX PHY). The above is also described in DP Standard v2.0 under 3.6.6.1. While at it simplify and add the LTTPR that is link trained to the debug message in intel_dp_set_signal_levels(). Fixes: b30edfd8d0 ("drm/i915: Switch to LTTPR non-transparent mode link training") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201229172201.4155327-2-imre.deak@intel.com		2021-01-13 17:22:14 +02:00
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drm	drm/i915/dp: Fix LTTPR vswing/pre-emp setting in non-transparent mode	2021-01-13 17:22:14 +02:00
host1x	gpu/host1x: bus: Add missing description for 'driver'	2020-11-05 22:12:55 +01:00
ipu-v3	gpu/ipu-v3/ipu-di: Strip out 2 unused 'di_sync_config' entries	2021-01-04 12:54:18 +01:00
trace
vga	pci-v5.11-changes	2020-12-15 16:49:59 -08:00
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