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Create an environment for CXL plumbing unit tests. Especially when it comes to an algorithm for HDM Decoder (Host-managed Device Memory Decoder) programming, the availability of an in-kernel-tree emulation environment for CXL configuration complexity and corner cases speeds development and deters regressions. The approach taken mirrors what was done for tools/testing/nvdimm/. I.e. an external module, cxl_test.ko built out of the tools/testing/cxl/ directory, provides mock implementations of kernel APIs and kernel objects to simulate a real world device hierarchy. One feedback for the tools/testing/nvdimm/ proposal was "why not do this in QEMU?". In fact, the CXL development community has developed a QEMU model for CXL [1]. However, there are a few blocking issues that keep QEMU from being a tight fit for topology + provisioning unit tests: 1/ The QEMU community has yet to show interest in merging any of this support that has had patches on the list since November 2020. So, testing CXL to date involves building custom QEMU with out-of-tree patches. 2/ CXL mechanisms like cross-host-bridge interleave do not have a clear path to be emulated by QEMU without major infrastructure work. This is easier to achieve with the alloc_mock_res() approach taken in this patch to shortcut-define emulated system physical address ranges with interleave behavior. The QEMU enabling has been critical to get the driver off the ground, and may still move forward, but it does not address the ongoing needs of a regression testing environment and test driven development. This patch adds an ACPI CXL Platform definition with emulated CXL multi-ported host-bridges. A follow on patch adds emulated memory expander devices. Acked-by: Ben Widawsky <ben.widawsky@intel.com> Reported-by: Vishal Verma <vishal.l.verma@intel.com> Link: https://lore.kernel.org/r/20210202005948.241655-1-ben.widawsky@intel.com [1] Link: https://lore.kernel.org/r/163164680798.2831381.838684634806668012.stgit@dwillia2-desk3.amr.corp.intel.com Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
37 lines
903 B
Makefile
37 lines
903 B
Makefile
# SPDX-License-Identifier: GPL-2.0
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ldflags-y += --wrap=is_acpi_device_node
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ldflags-y += --wrap=acpi_get_table
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ldflags-y += --wrap=acpi_put_table
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ldflags-y += --wrap=acpi_evaluate_integer
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ldflags-y += --wrap=acpi_pci_find_root
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ldflags-y += --wrap=pci_walk_bus
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ldflags-y += --wrap=nvdimm_bus_register
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DRIVERS := ../../../drivers
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CXL_SRC := $(DRIVERS)/cxl
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CXL_CORE_SRC := $(DRIVERS)/cxl/core
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ccflags-y := -I$(srctree)/drivers/cxl/
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ccflags-y += -D__mock=__weak
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obj-m += cxl_acpi.o
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cxl_acpi-y := $(CXL_SRC)/acpi.o
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cxl_acpi-y += mock_acpi.o
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cxl_acpi-y += config_check.o
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obj-m += cxl_pmem.o
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cxl_pmem-y := $(CXL_SRC)/pmem.o
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cxl_pmem-y += config_check.o
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obj-m += cxl_core.o
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cxl_core-y := $(CXL_CORE_SRC)/bus.o
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cxl_core-y += $(CXL_CORE_SRC)/pmem.o
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cxl_core-y += $(CXL_CORE_SRC)/regs.o
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cxl_core-y += $(CXL_CORE_SRC)/memdev.o
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cxl_core-y += $(CXL_CORE_SRC)/mbox.o
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cxl_core-y += config_check.o
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obj-m += test/
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