Mark Rutland d12517dd09 arm64: errata: Expand speculative SSBS workaround (again) ... [ Upstream commit adeec61a47 ] A number of Arm Ltd CPUs suffer from errata whereby an MSR to the SSBS special-purpose register does not affect subsequent speculative instructions, permitting speculative store bypassing for a window of time. We worked around this for a number of CPUs in commits: * 7187bb7d0b ("arm64: errata: Add workaround for Arm errata 3194386 and 3312417") * 75b3c43eab ("arm64: errata: Expand speculative SSBS workaround") Since then, similar errata have been published for a number of other Arm Ltd CPUs, for which the same mitigation is sufficient. This is described in their respective Software Developer Errata Notice (SDEN) documents: * Cortex-A76 (MP052) SDEN v31.0, erratum 3324349 https://developer.arm.com/documentation/SDEN-885749/3100/ * Cortex-A77 (MP074) SDEN v19.0, erratum 3324348 https://developer.arm.com/documentation/SDEN-1152370/1900/ * Cortex-A78 (MP102) SDEN v21.0, erratum 3324344 https://developer.arm.com/documentation/SDEN-1401784/2100/ * Cortex-A78C (MP138) SDEN v16.0, erratum 3324346 https://developer.arm.com/documentation/SDEN-1707916/1600/ * Cortex-A78C (MP154) SDEN v10.0, erratum 3324347 https://developer.arm.com/documentation/SDEN-2004089/1000/ * Cortex-A725 (MP190) SDEN v5.0, erratum 3456106 https://developer.arm.com/documentation/SDEN-2832921/0500/ * Cortex-X1 (MP077) SDEN v21.0, erratum 3324344 https://developer.arm.com/documentation/SDEN-1401782/2100/ * Cortex-X1C (MP136) SDEN v16.0, erratum 3324346 https://developer.arm.com/documentation/SDEN-1707914/1600/ * Neoverse-N1 (MP050) SDEN v32.0, erratum 3324349 https://developer.arm.com/documentation/SDEN-885747/3200/ * Neoverse-V1 (MP076) SDEN v19.0, erratum 3324341 https://developer.arm.com/documentation/SDEN-1401781/1900/ Note that due to the manner in which Arm develops IP and tracks errata, some CPUs share a common erratum number and some CPUs have multiple erratum numbers for the same HW issue. On parts without SB, it is necessary to use ISB for the workaround. The spec_bar() macro used in the mitigation will expand to a "DSB SY; ISB" sequence in this case, which is sufficient on all affected parts. Enable the existing mitigation by adding the relevant MIDRs to erratum_spec_ssbs_list. The list is sorted alphanumerically (involving moving Neoverse-V3 after Neoverse-V2) so that this is easy to audit and potentially extend again in future. The Kconfig text is also updated to clarify the set of affected parts and the mitigation. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Will Deacon <will@kernel.org> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Acked-by: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20240801101803.1982459-4-mark.rutland@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> [ Mark: fix conflicts in silicon-errata.rst ] Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Sasha Levin <sashal@kernel.org>		2024-08-19 05:45:41 +02:00
..
acpi_object_usage.rst	Documentation: arm64/acpi : clarify arm64 support of IBFT	2021-03-22 12:43:20 +00:00
amu.rst	Documentation: Chinese translation of Documentation/arm64/amu.rst	2020-09-28 15:24:24 -06:00
arm-acpi.rst	arm64: Replace HTTP links with HTTPS ones	2020-07-23 14:04:37 -06:00
asymmetric-32bit.rst	Documentation: arm64: describe asymmetric 32-bit support	2021-08-20 12:33:07 +02:00
booting.rst	arm64: Document the requirement for SCR_EL3.HCE	2021-08-24 16:44:23 +01:00
cpu-feature-registers.rst	arm64: cpufeature: add HWCAP for FEAT_RPRES	2022-03-11 12:22:33 +01:00
elf_hwcaps.rst	arm64: cpufeature: add HWCAP for FEAT_RPRES	2022-03-11 12:22:33 +01:00
features.rst	docs: archis: add a per-architecture features list	2020-12-03 15:10:15 -07:00
hugetlbpage.rst	Documentation: Chinese translation of Documentation/arm64/hugetlbpage.rst	2020-10-21 15:15:17 -06:00
index.rst	Documentation: arm64: describe asymmetric 32-bit support	2021-08-20 12:33:07 +02:00
kasan-offsets.sh	arm64: mm: extend linear region for 52-bit VA configurations	2020-11-09 17:15:37 +00:00
legacy_instructions.rst	docs: arm64: convert docs to ReST and rename to .rst	2019-06-14 14:20:27 -06:00
memory-tagging-extension.rst	Documentation: document the preferred tag checking mode feature	2021-07-28 18:39:26 +01:00
memory.rst	ARM:	2020-12-20 10:44:05 -08:00
perf.rst	Documentation: Chinese translation of Documentation/arm64/perf.rst	2020-11-13 15:21:38 -07:00
pointer-authentication.rst	arm64: Introduce prctl(PR_PAC_{SET,GET}_ENABLED_KEYS)	2021-04-13 17:31:44 +01:00
silicon-errata.rst	arm64: errata: Expand speculative SSBS workaround (again)	2024-08-19 05:45:41 +02:00
sve.rst	It's been a busy cycle for documentation - hopefully the busiest for a	2020-08-04 22:47:54 -07:00
tagged-address-abi.rst	userfaultfd: do not untag user pointers	2021-07-23 17:43:28 -07:00
tagged-pointers.rst	arm64: expose FAR_EL1 tag bits in siginfo	2020-11-23 18:17:39 +00:00