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Svpbmt (the S should be capitalized) is the "Supervisor-mode: page-based memory types" extension that specifies attributes for cacheability, idempotency and ordering. The relevant settings are done in special bits in PTEs: Here is the svpbmt PTE format: | 63 | 62-61 | 60-8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 N MT RSW D A G U X W R V ^ Of the Reserved bits [63:54] in a leaf PTE, the high bit is already allocated (as the N bit), so bits [62:61] are used as the MT (aka MemType) field. This field specifies one of three memory types that are close equivalents (or equivalent in effect) to the three main x86 and ARMv8 memory types - as shown in the following table. RISC-V Encoding & MemType RISC-V Description ---------- ------------------------------------------------ 00 - PMA Normal Cacheable, No change to implied PMA memory type 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory 11 - Rsvd Reserved for future standard use As the extension will not be present on all implementations, implement a method to handle cpufeatures via alternatives to not incur runtime penalties on cpu variants not supporting specific extensions and patch relevant code parts at runtime. Co-developed-by: Wei Fu <wefu@redhat.com> Signed-off-by: Wei Fu <wefu@redhat.com> Co-developed-by: Liu Shaohua <liush@allwinnertech.com> Signed-off-by: Liu Shaohua <liush@allwinnertech.com> Co-developed-by: Guo Ren <guoren@kernel.org> Signed-off-by: Guo Ren <guoren@kernel.org> [moved to use the alternatives mechanism] Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Link: https://lore.kernel.org/r/20220511192921.2223629-10-heiko@sntech.de Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
39 lines
1.2 KiB
C
39 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_PGTABLE_BITS_H
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#define _ASM_RISCV_PGTABLE_BITS_H
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#define _PAGE_ACCESSED_OFFSET 6
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#define _PAGE_PRESENT (1 << 0)
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#define _PAGE_READ (1 << 1) /* Readable */
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#define _PAGE_WRITE (1 << 2) /* Writable */
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#define _PAGE_EXEC (1 << 3) /* Executable */
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#define _PAGE_USER (1 << 4) /* User */
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#define _PAGE_GLOBAL (1 << 5) /* Global */
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#define _PAGE_ACCESSED (1 << 6) /* Set by hardware on any access */
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#define _PAGE_DIRTY (1 << 7) /* Set by hardware on any write */
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#define _PAGE_SOFT (1 << 8) /* Reserved for software */
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#define _PAGE_SPECIAL _PAGE_SOFT
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#define _PAGE_TABLE _PAGE_PRESENT
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/*
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* _PAGE_PROT_NONE is set on not-present pages (and ignored by the hardware) to
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* distinguish them from swapped out pages
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*/
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#define _PAGE_PROT_NONE _PAGE_GLOBAL
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#define _PAGE_PFN_SHIFT 10
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/*
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* when all of R/W/X are zero, the PTE is a pointer to the next level
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* of the page table; otherwise, it is a leaf PTE.
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*/
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#define _PAGE_LEAF (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)
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#endif /* _ASM_RISCV_PGTABLE_BITS_H */
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