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0793448187
Convert the device_is_tx_complete() operation on the DMA engine to a generic device_tx_status()operation which can return three states, DMA_TX_RUNNING, DMA_TX_COMPLETE, DMA_TX_PAUSED. [dan.j.williams@intel.com: update for timberdale] Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Cc: Maciej Sosnowski <maciej.sosnowski@intel.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Pavel Machek <pavel@ucw.cz> Cc: Li Yang <leoli@freescale.com> Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Cc: Magnus Damm <damm@opensource.se> Cc: Liam Girdwood <lrg@slimlogic.co.uk> Cc: Joe Perches <joe@perches.com> Cc: Roland Dreier <rdreier@cisco.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
261 lines
9.4 KiB
C
261 lines
9.4 KiB
C
/*
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*
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* include/linux/coh901318.h
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*
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*
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* Copyright (C) 2007-2009 ST-Ericsson
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* License terms: GNU General Public License (GPL) version 2
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* DMA driver for COH 901 318
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* Author: Per Friden <per.friden@stericsson.com>
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*/
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#ifndef COH901318_H
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#define COH901318_H
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#include <linux/device.h>
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#include <linux/dmaengine.h>
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#define MAX_DMA_PACKET_SIZE_SHIFT 11
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#define MAX_DMA_PACKET_SIZE (1 << MAX_DMA_PACKET_SIZE_SHIFT)
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/**
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* struct coh901318_lli - linked list item for DMAC
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* @control: control settings for DMAC
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* @src_addr: transfer source address
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* @dst_addr: transfer destination address
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* @link_addr: physical address to next lli
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* @virt_link_addr: virtual addres of next lli (only used by pool_free)
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* @phy_this: physical address of current lli (only used by pool_free)
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*/
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struct coh901318_lli {
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u32 control;
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dma_addr_t src_addr;
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dma_addr_t dst_addr;
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dma_addr_t link_addr;
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void *virt_link_addr;
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dma_addr_t phy_this;
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};
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/**
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* struct coh901318_params - parameters for DMAC configuration
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* @config: DMA config register
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* @ctrl_lli_last: DMA control register for the last lli in the list
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* @ctrl_lli: DMA control register for an lli
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* @ctrl_lli_chained: DMA control register for a chained lli
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*/
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struct coh901318_params {
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u32 config;
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u32 ctrl_lli_last;
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u32 ctrl_lli;
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u32 ctrl_lli_chained;
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};
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/**
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* struct coh_dma_channel - dma channel base
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* @name: ascii name of dma channel
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* @number: channel id number
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* @desc_nbr_max: number of preallocated descriptors
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* @priority_high: prio of channel, 0 low otherwise high.
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* @param: configuration parameters
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* @dev_addr: physical address of periphal connected to channel
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*/
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struct coh_dma_channel {
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const char name[32];
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const int number;
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const int desc_nbr_max;
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const int priority_high;
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const struct coh901318_params param;
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const dma_addr_t dev_addr;
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};
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/**
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* dma_access_memory_state_t - register dma for memory access
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*
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* @dev: The dma device
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* @active: 1 means dma intends to access memory
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* 0 means dma wont access memory
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*/
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typedef void (*dma_access_memory_state_t)(struct device *dev,
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bool active);
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/**
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* struct powersave - DMA power save structure
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* @lock: lock protecting data in this struct
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* @started_channels: bit mask indicating active dma channels
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*/
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struct powersave {
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spinlock_t lock;
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u64 started_channels;
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};
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/**
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* struct coh901318_platform - platform arch structure
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* @chans_slave: specifying dma slave channels
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* @chans_memcpy: specifying dma memcpy channels
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* @access_memory_state: requesting DMA memeory access (on / off)
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* @chan_conf: dma channel configurations
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* @max_channels: max number of dma chanenls
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*/
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struct coh901318_platform {
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const int *chans_slave;
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const int *chans_memcpy;
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const dma_access_memory_state_t access_memory_state;
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const struct coh_dma_channel *chan_conf;
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const int max_channels;
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};
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/**
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* coh901318_filter_id() - DMA channel filter function
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* @chan: dma channel handle
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* @chan_id: id of dma channel to be filter out
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*
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* In dma_request_channel() it specifies what channel id to be requested
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*/
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bool coh901318_filter_id(struct dma_chan *chan, void *chan_id);
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/*
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* DMA Controller - this access the static mappings of the coh901318 dma.
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*
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*/
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#define COH901318_MOD32_MASK (0x1F)
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#define COH901318_WORD_MASK (0xFFFFFFFF)
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/* INT_STATUS - Interrupt Status Registers 32bit (R/-) */
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#define COH901318_INT_STATUS1 (0x0000)
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#define COH901318_INT_STATUS2 (0x0004)
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/* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */
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#define COH901318_TC_INT_STATUS1 (0x0008)
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#define COH901318_TC_INT_STATUS2 (0x000C)
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/* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */
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#define COH901318_TC_INT_CLEAR1 (0x0010)
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#define COH901318_TC_INT_CLEAR2 (0x0014)
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/* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
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#define COH901318_RAW_TC_INT_STATUS1 (0x0018)
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#define COH901318_RAW_TC_INT_STATUS2 (0x001C)
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/* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */
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#define COH901318_BE_INT_STATUS1 (0x0020)
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#define COH901318_BE_INT_STATUS2 (0x0024)
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/* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */
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#define COH901318_BE_INT_CLEAR1 (0x0028)
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#define COH901318_BE_INT_CLEAR2 (0x002C)
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/* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
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#define COH901318_RAW_BE_INT_STATUS1 (0x0030)
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#define COH901318_RAW_BE_INT_STATUS2 (0x0034)
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/*
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* CX_CFG - Channel Configuration Registers 32bit (R/W)
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*/
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#define COH901318_CX_CFG (0x0100)
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#define COH901318_CX_CFG_SPACING (0x04)
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/* Channel enable activates tha dma job */
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#define COH901318_CX_CFG_CH_ENABLE (0x00000001)
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#define COH901318_CX_CFG_CH_DISABLE (0x00000000)
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/* Request Mode */
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#define COH901318_CX_CFG_RM_MASK (0x00000006)
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#define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY (0x0 << 1)
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#define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY (0x1 << 1)
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#define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY (0x1 << 1)
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#define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY (0x3 << 1)
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#define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY (0x3 << 1)
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/* Linked channel request field. RM must == 11 */
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#define COH901318_CX_CFG_LCRF_SHIFT 3
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#define COH901318_CX_CFG_LCRF_MASK (0x000001F8)
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#define COH901318_CX_CFG_LCR_DISABLE (0x00000000)
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/* Terminal Counter Interrupt Request Mask */
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#define COH901318_CX_CFG_TC_IRQ_ENABLE (0x00000200)
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#define COH901318_CX_CFG_TC_IRQ_DISABLE (0x00000000)
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/* Bus Error interrupt Mask */
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#define COH901318_CX_CFG_BE_IRQ_ENABLE (0x00000400)
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#define COH901318_CX_CFG_BE_IRQ_DISABLE (0x00000000)
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/*
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* CX_STAT - Channel Status Registers 32bit (R/-)
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*/
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#define COH901318_CX_STAT (0x0200)
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#define COH901318_CX_STAT_SPACING (0x04)
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#define COH901318_CX_STAT_RBE_IRQ_IND (0x00000008)
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#define COH901318_CX_STAT_RTC_IRQ_IND (0x00000004)
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#define COH901318_CX_STAT_ACTIVE (0x00000002)
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#define COH901318_CX_STAT_ENABLED (0x00000001)
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/*
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* CX_CTRL - Channel Control Registers 32bit (R/W)
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*/
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#define COH901318_CX_CTRL (0x0400)
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#define COH901318_CX_CTRL_SPACING (0x10)
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/* Transfer Count Enable */
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#define COH901318_CX_CTRL_TC_ENABLE (0x00001000)
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#define COH901318_CX_CTRL_TC_DISABLE (0x00000000)
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/* Transfer Count Value 0 - 4095 */
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#define COH901318_CX_CTRL_TC_VALUE_MASK (0x00000FFF)
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/* Burst count */
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#define COH901318_CX_CTRL_BURST_COUNT_MASK (0x0000E000)
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#define COH901318_CX_CTRL_BURST_COUNT_64_BYTES (0x7 << 13)
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#define COH901318_CX_CTRL_BURST_COUNT_48_BYTES (0x6 << 13)
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#define COH901318_CX_CTRL_BURST_COUNT_32_BYTES (0x5 << 13)
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#define COH901318_CX_CTRL_BURST_COUNT_16_BYTES (0x4 << 13)
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#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES (0x3 << 13)
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#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES (0x2 << 13)
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#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES (0x1 << 13)
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#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE (0x0 << 13)
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/* Source bus size */
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#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK (0x00030000)
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#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS (0x2 << 16)
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#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS (0x1 << 16)
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#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS (0x0 << 16)
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/* Source address increment */
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#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE (0x00040000)
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#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE (0x00000000)
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/* Destination Bus Size */
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#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK (0x00180000)
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#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS (0x2 << 19)
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#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS (0x1 << 19)
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#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS (0x0 << 19)
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/* Destination address increment */
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#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE (0x00200000)
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#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE (0x00000000)
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/* Master Mode (Master2 is only connected to MSL) */
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#define COH901318_CX_CTRL_MASTER_MODE_MASK (0x00C00000)
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#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W (0x3 << 22)
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#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W (0x2 << 22)
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#define COH901318_CX_CTRL_MASTER_MODE_M2RW (0x1 << 22)
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#define COH901318_CX_CTRL_MASTER_MODE_M1RW (0x0 << 22)
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/* Terminal Count flag to PER enable */
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#define COH901318_CX_CTRL_TCP_ENABLE (0x01000000)
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#define COH901318_CX_CTRL_TCP_DISABLE (0x00000000)
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/* Terminal Count flags to CPU enable */
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#define COH901318_CX_CTRL_TC_IRQ_ENABLE (0x02000000)
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#define COH901318_CX_CTRL_TC_IRQ_DISABLE (0x00000000)
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/* Hand shake to peripheral */
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#define COH901318_CX_CTRL_HSP_ENABLE (0x04000000)
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#define COH901318_CX_CTRL_HSP_DISABLE (0x00000000)
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#define COH901318_CX_CTRL_HSS_ENABLE (0x08000000)
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#define COH901318_CX_CTRL_HSS_DISABLE (0x00000000)
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/* DMA mode */
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#define COH901318_CX_CTRL_DDMA_MASK (0x30000000)
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#define COH901318_CX_CTRL_DDMA_LEGACY (0x0 << 28)
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#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1 (0x1 << 28)
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#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2 (0x2 << 28)
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/* Primary Request Data Destination */
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#define COH901318_CX_CTRL_PRDD_MASK (0x40000000)
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#define COH901318_CX_CTRL_PRDD_DEST (0x1 << 30)
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#define COH901318_CX_CTRL_PRDD_SOURCE (0x0 << 30)
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/*
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* CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)
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*/
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#define COH901318_CX_SRC_ADDR (0x0404)
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#define COH901318_CX_SRC_ADDR_SPACING (0x10)
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/*
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* CX_DST_ADDR - Channel Destination Address Registers 32bit R/W
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*/
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#define COH901318_CX_DST_ADDR (0x0408)
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#define COH901318_CX_DST_ADDR_SPACING (0x10)
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/*
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* CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)
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*/
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#define COH901318_CX_LNK_ADDR (0x040C)
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#define COH901318_CX_LNK_ADDR_SPACING (0x10)
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#define COH901318_CX_LNK_LINK_IMMEDIATE (0x00000001)
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#endif /* COH901318_H */
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