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Add the low-level API that allows to manage DPSECI DPAA2 objects that sit on the Management Complex (MC) fsl-mc bus. The API is compatible with MC firmware 10.2.0+. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
150 lines
3.4 KiB
C
150 lines
3.4 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
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/*
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* Copyright 2013-2016 Freescale Semiconductor Inc.
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* Copyright 2017-2018 NXP
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*/
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#ifndef _DPSECI_CMD_H_
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#define _DPSECI_CMD_H_
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/* DPSECI Version */
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#define DPSECI_VER_MAJOR 5
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#define DPSECI_VER_MINOR 3
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#define DPSECI_VER(maj, min) (((maj) << 16) | (min))
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#define DPSECI_VERSION DPSECI_VER(DPSECI_VER_MAJOR, DPSECI_VER_MINOR)
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/* Command versioning */
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#define DPSECI_CMD_BASE_VERSION 1
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#define DPSECI_CMD_BASE_VERSION_V2 2
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#define DPSECI_CMD_ID_OFFSET 4
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#define DPSECI_CMD_V1(id) (((id) << DPSECI_CMD_ID_OFFSET) | \
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DPSECI_CMD_BASE_VERSION)
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#define DPSECI_CMD_V2(id) (((id) << DPSECI_CMD_ID_OFFSET) | \
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DPSECI_CMD_BASE_VERSION_V2)
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/* Command IDs */
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#define DPSECI_CMDID_CLOSE DPSECI_CMD_V1(0x800)
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#define DPSECI_CMDID_OPEN DPSECI_CMD_V1(0x809)
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#define DPSECI_CMDID_GET_API_VERSION DPSECI_CMD_V1(0xa09)
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#define DPSECI_CMDID_ENABLE DPSECI_CMD_V1(0x002)
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#define DPSECI_CMDID_DISABLE DPSECI_CMD_V1(0x003)
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#define DPSECI_CMDID_GET_ATTR DPSECI_CMD_V1(0x004)
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#define DPSECI_CMDID_IS_ENABLED DPSECI_CMD_V1(0x006)
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#define DPSECI_CMDID_SET_RX_QUEUE DPSECI_CMD_V1(0x194)
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#define DPSECI_CMDID_GET_RX_QUEUE DPSECI_CMD_V1(0x196)
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#define DPSECI_CMDID_GET_TX_QUEUE DPSECI_CMD_V1(0x197)
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#define DPSECI_CMDID_GET_SEC_ATTR DPSECI_CMD_V2(0x198)
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#define DPSECI_CMDID_SET_CONGESTION_NOTIFICATION DPSECI_CMD_V1(0x170)
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#define DPSECI_CMDID_GET_CONGESTION_NOTIFICATION DPSECI_CMD_V1(0x171)
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/* Macros for accessing command fields smaller than 1 byte */
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#define DPSECI_MASK(field) \
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GENMASK(DPSECI_##field##_SHIFT + DPSECI_##field##_SIZE - 1, \
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DPSECI_##field##_SHIFT)
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#define dpseci_set_field(var, field, val) \
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((var) |= (((val) << DPSECI_##field##_SHIFT) & DPSECI_MASK(field)))
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#define dpseci_get_field(var, field) \
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(((var) & DPSECI_MASK(field)) >> DPSECI_##field##_SHIFT)
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struct dpseci_cmd_open {
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__le32 dpseci_id;
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};
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#define DPSECI_ENABLE_SHIFT 0
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#define DPSECI_ENABLE_SIZE 1
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struct dpseci_rsp_is_enabled {
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u8 is_enabled;
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};
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struct dpseci_rsp_get_attributes {
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__le32 id;
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__le32 pad0;
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u8 num_tx_queues;
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u8 num_rx_queues;
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u8 pad1[6];
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__le32 options;
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};
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#define DPSECI_DEST_TYPE_SHIFT 0
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#define DPSECI_DEST_TYPE_SIZE 4
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#define DPSECI_ORDER_PRESERVATION_SHIFT 0
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#define DPSECI_ORDER_PRESERVATION_SIZE 1
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struct dpseci_cmd_queue {
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__le32 dest_id;
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u8 priority;
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u8 queue;
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u8 dest_type;
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u8 pad;
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__le64 user_ctx;
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union {
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__le32 options;
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__le32 fqid;
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};
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u8 order_preservation_en;
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};
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struct dpseci_rsp_get_tx_queue {
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__le32 pad;
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__le32 fqid;
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u8 priority;
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};
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struct dpseci_rsp_get_sec_attr {
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__le16 ip_id;
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u8 major_rev;
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u8 minor_rev;
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u8 era;
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u8 pad0[3];
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u8 deco_num;
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u8 zuc_auth_acc_num;
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u8 zuc_enc_acc_num;
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u8 pad1;
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u8 snow_f8_acc_num;
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u8 snow_f9_acc_num;
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u8 crc_acc_num;
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u8 pad2;
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u8 pk_acc_num;
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u8 kasumi_acc_num;
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u8 rng_acc_num;
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u8 pad3;
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u8 md_acc_num;
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u8 arc4_acc_num;
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u8 des_acc_num;
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u8 aes_acc_num;
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u8 ccha_acc_num;
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u8 ptha_acc_num;
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};
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struct dpseci_rsp_get_api_version {
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__le16 major;
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__le16 minor;
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};
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#define DPSECI_CGN_DEST_TYPE_SHIFT 0
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#define DPSECI_CGN_DEST_TYPE_SIZE 4
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#define DPSECI_CGN_UNITS_SHIFT 4
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#define DPSECI_CGN_UNITS_SIZE 2
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struct dpseci_cmd_congestion_notification {
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__le32 dest_id;
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__le16 notification_mode;
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u8 priority;
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u8 options;
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__le64 message_iova;
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__le64 message_ctx;
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__le32 threshold_entry;
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__le32 threshold_exit;
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};
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#endif /* _DPSECI_CMD_H_ */
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