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66dd347470
The function detect_harden_bp_fw() is gone after commitd4647f0a2a
("arm64: Rewrite Spectre-v2 mitigation code"). Update this comment to reflect the new state of affairs. Fixes:d4647f0a2a
("arm64: Rewrite Spectre-v2 mitigation code") Signed-off-by: Stephen Boyd <swboyd@chromium.org> Cc: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20201020214544.3206838-3-swboyd@chromium.org Signed-off-by: Will Deacon <will@kernel.org>
791 lines
20 KiB
C
791 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Handle detection, reporting and mitigation of Spectre v1, v2 and v4, as
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* detailed at:
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*
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* https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability
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*
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* This code was originally written hastily under an awful lot of stress and so
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* aspects of it are somewhat hacky. Unfortunately, changing anything in here
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* instantly makes me feel ill. Thanks, Jann. Thann.
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*
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* Copyright (C) 2018 ARM Ltd, All Rights Reserved.
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* Copyright (C) 2020 Google LLC
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*
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* "If there's something strange in your neighbourhood, who you gonna call?"
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*
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* Authors: Will Deacon <will@kernel.org> and Marc Zyngier <maz@kernel.org>
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*/
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#include <linux/arm-smccc.h>
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#include <linux/cpu.h>
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#include <linux/device.h>
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#include <linux/nospec.h>
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#include <linux/prctl.h>
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#include <linux/sched/task_stack.h>
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#include <asm/spectre.h>
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#include <asm/traps.h>
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/*
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* We try to ensure that the mitigation state can never change as the result of
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* onlining a late CPU.
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*/
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static void update_mitigation_state(enum mitigation_state *oldp,
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enum mitigation_state new)
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{
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enum mitigation_state state;
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do {
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state = READ_ONCE(*oldp);
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if (new <= state)
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break;
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/* Userspace almost certainly can't deal with this. */
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if (WARN_ON(system_capabilities_finalized()))
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break;
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} while (cmpxchg_relaxed(oldp, state, new) != state);
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}
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/*
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* Spectre v1.
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*
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* The kernel can't protect userspace for this one: it's each person for
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* themselves. Advertise what we're doing and be done with it.
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*/
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ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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return sprintf(buf, "Mitigation: __user pointer sanitization\n");
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}
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/*
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* Spectre v2.
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*
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* This one sucks. A CPU is either:
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*
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* - Mitigated in hardware and advertised by ID_AA64PFR0_EL1.CSV2.
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* - Mitigated in hardware and listed in our "safe list".
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* - Mitigated in software by firmware.
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* - Mitigated in software by a CPU-specific dance in the kernel and a
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* firmware call at EL2.
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* - Vulnerable.
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*
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* It's not unlikely for different CPUs in a big.LITTLE system to fall into
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* different camps.
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*/
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static enum mitigation_state spectre_v2_state;
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static bool __read_mostly __nospectre_v2;
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static int __init parse_spectre_v2_param(char *str)
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{
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__nospectre_v2 = true;
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return 0;
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}
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early_param("nospectre_v2", parse_spectre_v2_param);
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static bool spectre_v2_mitigations_off(void)
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{
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bool ret = __nospectre_v2 || cpu_mitigations_off();
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if (ret)
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pr_info_once("spectre-v2 mitigation disabled by command line option\n");
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return ret;
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}
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ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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switch (spectre_v2_state) {
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case SPECTRE_UNAFFECTED:
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return sprintf(buf, "Not affected\n");
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case SPECTRE_MITIGATED:
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return sprintf(buf, "Mitigation: Branch predictor hardening\n");
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case SPECTRE_VULNERABLE:
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fallthrough;
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default:
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return sprintf(buf, "Vulnerable\n");
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}
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}
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static enum mitigation_state spectre_v2_get_cpu_hw_mitigation_state(void)
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{
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u64 pfr0;
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static const struct midr_range spectre_v2_safe_list[] = {
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
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MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
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MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
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MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
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MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
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{ /* sentinel */ }
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};
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/* If the CPU has CSV2 set, we're safe */
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pfr0 = read_cpuid(ID_AA64PFR0_EL1);
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if (cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_CSV2_SHIFT))
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return SPECTRE_UNAFFECTED;
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/* Alternatively, we have a list of unaffected CPUs */
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if (is_midr_in_range_list(read_cpuid_id(), spectre_v2_safe_list))
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return SPECTRE_UNAFFECTED;
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return SPECTRE_VULNERABLE;
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}
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#define SMCCC_ARCH_WORKAROUND_RET_UNAFFECTED (1)
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static enum mitigation_state spectre_v2_get_cpu_fw_mitigation_state(void)
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{
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int ret;
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struct arm_smccc_res res;
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arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
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ARM_SMCCC_ARCH_WORKAROUND_1, &res);
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ret = res.a0;
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switch (ret) {
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case SMCCC_RET_SUCCESS:
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return SPECTRE_MITIGATED;
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case SMCCC_ARCH_WORKAROUND_RET_UNAFFECTED:
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return SPECTRE_UNAFFECTED;
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default:
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fallthrough;
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case SMCCC_RET_NOT_SUPPORTED:
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return SPECTRE_VULNERABLE;
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}
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}
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bool has_spectre_v2(const struct arm64_cpu_capabilities *entry, int scope)
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{
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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if (spectre_v2_get_cpu_hw_mitigation_state() == SPECTRE_UNAFFECTED)
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return false;
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if (spectre_v2_get_cpu_fw_mitigation_state() == SPECTRE_UNAFFECTED)
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return false;
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return true;
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}
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DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);
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enum mitigation_state arm64_get_spectre_v2_state(void)
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{
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return spectre_v2_state;
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}
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#ifdef CONFIG_KVM
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#include <asm/cacheflush.h>
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#include <asm/kvm_asm.h>
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atomic_t arm64_el2_vector_last_slot = ATOMIC_INIT(-1);
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static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start,
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const char *hyp_vecs_end)
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{
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void *dst = lm_alias(__bp_harden_hyp_vecs + slot * SZ_2K);
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int i;
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for (i = 0; i < SZ_2K; i += 0x80)
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memcpy(dst + i, hyp_vecs_start, hyp_vecs_end - hyp_vecs_start);
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__flush_icache_range((uintptr_t)dst, (uintptr_t)dst + SZ_2K);
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}
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static void install_bp_hardening_cb(bp_hardening_cb_t fn)
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{
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static DEFINE_RAW_SPINLOCK(bp_lock);
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int cpu, slot = -1;
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const char *hyp_vecs_start = __smccc_workaround_1_smc;
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const char *hyp_vecs_end = __smccc_workaround_1_smc +
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__SMCCC_WORKAROUND_1_SMC_SZ;
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/*
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* Vinz Clortho takes the hyp_vecs start/end "keys" at
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* the door when we're a guest. Skip the hyp-vectors work.
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*/
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if (!is_hyp_mode_available()) {
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__this_cpu_write(bp_hardening_data.fn, fn);
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return;
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}
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raw_spin_lock(&bp_lock);
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for_each_possible_cpu(cpu) {
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if (per_cpu(bp_hardening_data.fn, cpu) == fn) {
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slot = per_cpu(bp_hardening_data.hyp_vectors_slot, cpu);
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break;
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}
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}
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if (slot == -1) {
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slot = atomic_inc_return(&arm64_el2_vector_last_slot);
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BUG_ON(slot >= BP_HARDEN_EL2_SLOTS);
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__copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end);
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}
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__this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot);
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__this_cpu_write(bp_hardening_data.fn, fn);
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raw_spin_unlock(&bp_lock);
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}
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#else
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static void install_bp_hardening_cb(bp_hardening_cb_t fn)
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{
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__this_cpu_write(bp_hardening_data.fn, fn);
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}
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#endif /* CONFIG_KVM */
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static void call_smc_arch_workaround_1(void)
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{
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arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
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}
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static void call_hvc_arch_workaround_1(void)
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{
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arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
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}
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static void qcom_link_stack_sanitisation(void)
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{
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u64 tmp;
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asm volatile("mov %0, x30 \n"
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".rept 16 \n"
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"bl . + 4 \n"
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".endr \n"
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"mov x30, %0 \n"
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: "=&r" (tmp));
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}
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static bp_hardening_cb_t spectre_v2_get_sw_mitigation_cb(void)
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{
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u32 midr = read_cpuid_id();
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if (((midr & MIDR_CPU_MODEL_MASK) != MIDR_QCOM_FALKOR) &&
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((midr & MIDR_CPU_MODEL_MASK) != MIDR_QCOM_FALKOR_V1))
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return NULL;
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return qcom_link_stack_sanitisation;
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}
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static enum mitigation_state spectre_v2_enable_fw_mitigation(void)
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{
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bp_hardening_cb_t cb;
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enum mitigation_state state;
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state = spectre_v2_get_cpu_fw_mitigation_state();
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if (state != SPECTRE_MITIGATED)
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return state;
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if (spectre_v2_mitigations_off())
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return SPECTRE_VULNERABLE;
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switch (arm_smccc_1_1_get_conduit()) {
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case SMCCC_CONDUIT_HVC:
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cb = call_hvc_arch_workaround_1;
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break;
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case SMCCC_CONDUIT_SMC:
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cb = call_smc_arch_workaround_1;
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break;
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default:
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return SPECTRE_VULNERABLE;
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}
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/*
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* Prefer a CPU-specific workaround if it exists. Note that we
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* still rely on firmware for the mitigation at EL2.
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*/
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cb = spectre_v2_get_sw_mitigation_cb() ?: cb;
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install_bp_hardening_cb(cb);
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return SPECTRE_MITIGATED;
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}
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void spectre_v2_enable_mitigation(const struct arm64_cpu_capabilities *__unused)
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{
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enum mitigation_state state;
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WARN_ON(preemptible());
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state = spectre_v2_get_cpu_hw_mitigation_state();
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if (state == SPECTRE_VULNERABLE)
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state = spectre_v2_enable_fw_mitigation();
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update_mitigation_state(&spectre_v2_state, state);
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}
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/*
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* Spectre v4.
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*
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* If you thought Spectre v2 was nasty, wait until you see this mess. A CPU is
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* either:
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*
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* - Mitigated in hardware and listed in our "safe list".
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* - Mitigated in hardware via PSTATE.SSBS.
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* - Mitigated in software by firmware (sometimes referred to as SSBD).
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*
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* Wait, that doesn't sound so bad, does it? Keep reading...
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*
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* A major source of headaches is that the software mitigation is enabled both
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* on a per-task basis, but can also be forced on for the kernel, necessitating
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* both context-switch *and* entry/exit hooks. To make it even worse, some CPUs
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* allow EL0 to toggle SSBS directly, which can end up with the prctl() state
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* being stale when re-entering the kernel. The usual big.LITTLE caveats apply,
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* so you can have systems that have both firmware and SSBS mitigations. This
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* means we actually have to reject late onlining of CPUs with mitigations if
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* all of the currently onlined CPUs are safelisted, as the mitigation tends to
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* be opt-in for userspace. Yes, really, the cure is worse than the disease.
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*
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* The only good part is that if the firmware mitigation is present, then it is
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* present for all CPUs, meaning we don't have to worry about late onlining of a
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* vulnerable CPU if one of the boot CPUs is using the firmware mitigation.
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*
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* Give me a VAX-11/780 any day of the week...
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*/
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static enum mitigation_state spectre_v4_state;
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/* This is the per-cpu state tracking whether we need to talk to firmware */
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DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required);
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enum spectre_v4_policy {
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SPECTRE_V4_POLICY_MITIGATION_DYNAMIC,
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SPECTRE_V4_POLICY_MITIGATION_ENABLED,
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SPECTRE_V4_POLICY_MITIGATION_DISABLED,
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};
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static enum spectre_v4_policy __read_mostly __spectre_v4_policy;
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static const struct spectre_v4_param {
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const char *str;
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enum spectre_v4_policy policy;
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} spectre_v4_params[] = {
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{ "force-on", SPECTRE_V4_POLICY_MITIGATION_ENABLED, },
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{ "force-off", SPECTRE_V4_POLICY_MITIGATION_DISABLED, },
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{ "kernel", SPECTRE_V4_POLICY_MITIGATION_DYNAMIC, },
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};
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static int __init parse_spectre_v4_param(char *str)
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{
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int i;
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if (!str || !str[0])
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return -EINVAL;
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for (i = 0; i < ARRAY_SIZE(spectre_v4_params); i++) {
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const struct spectre_v4_param *param = &spectre_v4_params[i];
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if (strncmp(str, param->str, strlen(param->str)))
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continue;
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__spectre_v4_policy = param->policy;
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return 0;
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}
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return -EINVAL;
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}
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early_param("ssbd", parse_spectre_v4_param);
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/*
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* Because this was all written in a rush by people working in different silos,
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* we've ended up with multiple command line options to control the same thing.
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* Wrap these up in some helpers, which prefer disabling the mitigation if faced
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* with contradictory parameters. The mitigation is always either "off",
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* "dynamic" or "on".
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*/
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static bool spectre_v4_mitigations_off(void)
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{
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bool ret = cpu_mitigations_off() ||
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__spectre_v4_policy == SPECTRE_V4_POLICY_MITIGATION_DISABLED;
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if (ret)
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pr_info_once("spectre-v4 mitigation disabled by command-line option\n");
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return ret;
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}
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/* Do we need to toggle the mitigation state on entry to/exit from the kernel? */
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static bool spectre_v4_mitigations_dynamic(void)
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{
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return !spectre_v4_mitigations_off() &&
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__spectre_v4_policy == SPECTRE_V4_POLICY_MITIGATION_DYNAMIC;
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}
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static bool spectre_v4_mitigations_on(void)
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{
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return !spectre_v4_mitigations_off() &&
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__spectre_v4_policy == SPECTRE_V4_POLICY_MITIGATION_ENABLED;
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}
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ssize_t cpu_show_spec_store_bypass(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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switch (spectre_v4_state) {
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case SPECTRE_UNAFFECTED:
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return sprintf(buf, "Not affected\n");
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case SPECTRE_MITIGATED:
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return sprintf(buf, "Mitigation: Speculative Store Bypass disabled via prctl\n");
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case SPECTRE_VULNERABLE:
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fallthrough;
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default:
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return sprintf(buf, "Vulnerable\n");
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}
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}
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enum mitigation_state arm64_get_spectre_v4_state(void)
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{
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return spectre_v4_state;
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}
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static enum mitigation_state spectre_v4_get_cpu_hw_mitigation_state(void)
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{
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static const struct midr_range spectre_v4_safe_list[] = {
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
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MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
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MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
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MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
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{ /* sentinel */ },
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};
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if (is_midr_in_range_list(read_cpuid_id(), spectre_v4_safe_list))
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return SPECTRE_UNAFFECTED;
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/* CPU features are detected first */
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if (this_cpu_has_cap(ARM64_SSBS))
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return SPECTRE_MITIGATED;
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return SPECTRE_VULNERABLE;
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}
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static enum mitigation_state spectre_v4_get_cpu_fw_mitigation_state(void)
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{
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int ret;
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struct arm_smccc_res res;
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arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
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ARM_SMCCC_ARCH_WORKAROUND_2, &res);
|
|
|
|
ret = res.a0;
|
|
switch (ret) {
|
|
case SMCCC_RET_SUCCESS:
|
|
return SPECTRE_MITIGATED;
|
|
case SMCCC_ARCH_WORKAROUND_RET_UNAFFECTED:
|
|
fallthrough;
|
|
case SMCCC_RET_NOT_REQUIRED:
|
|
return SPECTRE_UNAFFECTED;
|
|
default:
|
|
fallthrough;
|
|
case SMCCC_RET_NOT_SUPPORTED:
|
|
return SPECTRE_VULNERABLE;
|
|
}
|
|
}
|
|
|
|
bool has_spectre_v4(const struct arm64_cpu_capabilities *cap, int scope)
|
|
{
|
|
enum mitigation_state state;
|
|
|
|
WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
|
|
|
|
state = spectre_v4_get_cpu_hw_mitigation_state();
|
|
if (state == SPECTRE_VULNERABLE)
|
|
state = spectre_v4_get_cpu_fw_mitigation_state();
|
|
|
|
return state != SPECTRE_UNAFFECTED;
|
|
}
|
|
|
|
static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
|
|
{
|
|
if (user_mode(regs))
|
|
return 1;
|
|
|
|
if (instr & BIT(PSTATE_Imm_shift))
|
|
regs->pstate |= PSR_SSBS_BIT;
|
|
else
|
|
regs->pstate &= ~PSR_SSBS_BIT;
|
|
|
|
arm64_skip_faulting_instruction(regs, 4);
|
|
return 0;
|
|
}
|
|
|
|
static struct undef_hook ssbs_emulation_hook = {
|
|
.instr_mask = ~(1U << PSTATE_Imm_shift),
|
|
.instr_val = 0xd500401f | PSTATE_SSBS,
|
|
.fn = ssbs_emulation_handler,
|
|
};
|
|
|
|
static enum mitigation_state spectre_v4_enable_hw_mitigation(void)
|
|
{
|
|
static bool undef_hook_registered = false;
|
|
static DEFINE_RAW_SPINLOCK(hook_lock);
|
|
enum mitigation_state state;
|
|
|
|
/*
|
|
* If the system is mitigated but this CPU doesn't have SSBS, then
|
|
* we must be on the safelist and there's nothing more to do.
|
|
*/
|
|
state = spectre_v4_get_cpu_hw_mitigation_state();
|
|
if (state != SPECTRE_MITIGATED || !this_cpu_has_cap(ARM64_SSBS))
|
|
return state;
|
|
|
|
raw_spin_lock(&hook_lock);
|
|
if (!undef_hook_registered) {
|
|
register_undef_hook(&ssbs_emulation_hook);
|
|
undef_hook_registered = true;
|
|
}
|
|
raw_spin_unlock(&hook_lock);
|
|
|
|
if (spectre_v4_mitigations_off()) {
|
|
sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
|
|
asm volatile(SET_PSTATE_SSBS(1));
|
|
return SPECTRE_VULNERABLE;
|
|
}
|
|
|
|
/* SCTLR_EL1.DSSBS was initialised to 0 during boot */
|
|
asm volatile(SET_PSTATE_SSBS(0));
|
|
return SPECTRE_MITIGATED;
|
|
}
|
|
|
|
/*
|
|
* Patch a branch over the Spectre-v4 mitigation code with a NOP so that
|
|
* we fallthrough and check whether firmware needs to be called on this CPU.
|
|
*/
|
|
void __init spectre_v4_patch_fw_mitigation_enable(struct alt_instr *alt,
|
|
__le32 *origptr,
|
|
__le32 *updptr, int nr_inst)
|
|
{
|
|
BUG_ON(nr_inst != 1); /* Branch -> NOP */
|
|
|
|
if (spectre_v4_mitigations_off())
|
|
return;
|
|
|
|
if (cpus_have_final_cap(ARM64_SSBS))
|
|
return;
|
|
|
|
if (spectre_v4_mitigations_dynamic())
|
|
*updptr = cpu_to_le32(aarch64_insn_gen_nop());
|
|
}
|
|
|
|
/*
|
|
* Patch a NOP in the Spectre-v4 mitigation code with an SMC/HVC instruction
|
|
* to call into firmware to adjust the mitigation state.
|
|
*/
|
|
void __init spectre_v4_patch_fw_mitigation_conduit(struct alt_instr *alt,
|
|
__le32 *origptr,
|
|
__le32 *updptr, int nr_inst)
|
|
{
|
|
u32 insn;
|
|
|
|
BUG_ON(nr_inst != 1); /* NOP -> HVC/SMC */
|
|
|
|
switch (arm_smccc_1_1_get_conduit()) {
|
|
case SMCCC_CONDUIT_HVC:
|
|
insn = aarch64_insn_get_hvc_value();
|
|
break;
|
|
case SMCCC_CONDUIT_SMC:
|
|
insn = aarch64_insn_get_smc_value();
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
|
|
*updptr = cpu_to_le32(insn);
|
|
}
|
|
|
|
static enum mitigation_state spectre_v4_enable_fw_mitigation(void)
|
|
{
|
|
enum mitigation_state state;
|
|
|
|
state = spectre_v4_get_cpu_fw_mitigation_state();
|
|
if (state != SPECTRE_MITIGATED)
|
|
return state;
|
|
|
|
if (spectre_v4_mitigations_off()) {
|
|
arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_WORKAROUND_2, false, NULL);
|
|
return SPECTRE_VULNERABLE;
|
|
}
|
|
|
|
arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_WORKAROUND_2, true, NULL);
|
|
|
|
if (spectre_v4_mitigations_dynamic())
|
|
__this_cpu_write(arm64_ssbd_callback_required, 1);
|
|
|
|
return SPECTRE_MITIGATED;
|
|
}
|
|
|
|
void spectre_v4_enable_mitigation(const struct arm64_cpu_capabilities *__unused)
|
|
{
|
|
enum mitigation_state state;
|
|
|
|
WARN_ON(preemptible());
|
|
|
|
state = spectre_v4_enable_hw_mitigation();
|
|
if (state == SPECTRE_VULNERABLE)
|
|
state = spectre_v4_enable_fw_mitigation();
|
|
|
|
update_mitigation_state(&spectre_v4_state, state);
|
|
}
|
|
|
|
static void __update_pstate_ssbs(struct pt_regs *regs, bool state)
|
|
{
|
|
u64 bit = compat_user_mode(regs) ? PSR_AA32_SSBS_BIT : PSR_SSBS_BIT;
|
|
|
|
if (state)
|
|
regs->pstate |= bit;
|
|
else
|
|
regs->pstate &= ~bit;
|
|
}
|
|
|
|
void spectre_v4_enable_task_mitigation(struct task_struct *tsk)
|
|
{
|
|
struct pt_regs *regs = task_pt_regs(tsk);
|
|
bool ssbs = false, kthread = tsk->flags & PF_KTHREAD;
|
|
|
|
if (spectre_v4_mitigations_off())
|
|
ssbs = true;
|
|
else if (spectre_v4_mitigations_dynamic() && !kthread)
|
|
ssbs = !test_tsk_thread_flag(tsk, TIF_SSBD);
|
|
|
|
__update_pstate_ssbs(regs, ssbs);
|
|
}
|
|
|
|
/*
|
|
* The Spectre-v4 mitigation can be controlled via a prctl() from userspace.
|
|
* This is interesting because the "speculation disabled" behaviour can be
|
|
* configured so that it is preserved across exec(), which means that the
|
|
* prctl() may be necessary even when PSTATE.SSBS can be toggled directly
|
|
* from userspace.
|
|
*/
|
|
static void ssbd_prctl_enable_mitigation(struct task_struct *task)
|
|
{
|
|
task_clear_spec_ssb_noexec(task);
|
|
task_set_spec_ssb_disable(task);
|
|
set_tsk_thread_flag(task, TIF_SSBD);
|
|
}
|
|
|
|
static void ssbd_prctl_disable_mitigation(struct task_struct *task)
|
|
{
|
|
task_clear_spec_ssb_noexec(task);
|
|
task_clear_spec_ssb_disable(task);
|
|
clear_tsk_thread_flag(task, TIF_SSBD);
|
|
}
|
|
|
|
static int ssbd_prctl_set(struct task_struct *task, unsigned long ctrl)
|
|
{
|
|
switch (ctrl) {
|
|
case PR_SPEC_ENABLE:
|
|
/* Enable speculation: disable mitigation */
|
|
/*
|
|
* Force disabled speculation prevents it from being
|
|
* re-enabled.
|
|
*/
|
|
if (task_spec_ssb_force_disable(task))
|
|
return -EPERM;
|
|
|
|
/*
|
|
* If the mitigation is forced on, then speculation is forced
|
|
* off and we again prevent it from being re-enabled.
|
|
*/
|
|
if (spectre_v4_mitigations_on())
|
|
return -EPERM;
|
|
|
|
ssbd_prctl_disable_mitigation(task);
|
|
break;
|
|
case PR_SPEC_FORCE_DISABLE:
|
|
/* Force disable speculation: force enable mitigation */
|
|
/*
|
|
* If the mitigation is forced off, then speculation is forced
|
|
* on and we prevent it from being disabled.
|
|
*/
|
|
if (spectre_v4_mitigations_off())
|
|
return -EPERM;
|
|
|
|
task_set_spec_ssb_force_disable(task);
|
|
fallthrough;
|
|
case PR_SPEC_DISABLE:
|
|
/* Disable speculation: enable mitigation */
|
|
/* Same as PR_SPEC_FORCE_DISABLE */
|
|
if (spectre_v4_mitigations_off())
|
|
return -EPERM;
|
|
|
|
ssbd_prctl_enable_mitigation(task);
|
|
break;
|
|
case PR_SPEC_DISABLE_NOEXEC:
|
|
/* Disable speculation until execve(): enable mitigation */
|
|
/*
|
|
* If the mitigation state is forced one way or the other, then
|
|
* we must fail now before we try to toggle it on execve().
|
|
*/
|
|
if (task_spec_ssb_force_disable(task) ||
|
|
spectre_v4_mitigations_off() ||
|
|
spectre_v4_mitigations_on()) {
|
|
return -EPERM;
|
|
}
|
|
|
|
ssbd_prctl_enable_mitigation(task);
|
|
task_set_spec_ssb_noexec(task);
|
|
break;
|
|
default:
|
|
return -ERANGE;
|
|
}
|
|
|
|
spectre_v4_enable_task_mitigation(task);
|
|
return 0;
|
|
}
|
|
|
|
int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
|
|
unsigned long ctrl)
|
|
{
|
|
switch (which) {
|
|
case PR_SPEC_STORE_BYPASS:
|
|
return ssbd_prctl_set(task, ctrl);
|
|
default:
|
|
return -ENODEV;
|
|
}
|
|
}
|
|
|
|
static int ssbd_prctl_get(struct task_struct *task)
|
|
{
|
|
switch (spectre_v4_state) {
|
|
case SPECTRE_UNAFFECTED:
|
|
return PR_SPEC_NOT_AFFECTED;
|
|
case SPECTRE_MITIGATED:
|
|
if (spectre_v4_mitigations_on())
|
|
return PR_SPEC_NOT_AFFECTED;
|
|
|
|
if (spectre_v4_mitigations_dynamic())
|
|
break;
|
|
|
|
/* Mitigations are disabled, so we're vulnerable. */
|
|
fallthrough;
|
|
case SPECTRE_VULNERABLE:
|
|
fallthrough;
|
|
default:
|
|
return PR_SPEC_ENABLE;
|
|
}
|
|
|
|
/* Check the mitigation state for this task */
|
|
if (task_spec_ssb_force_disable(task))
|
|
return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
|
|
|
|
if (task_spec_ssb_noexec(task))
|
|
return PR_SPEC_PRCTL | PR_SPEC_DISABLE_NOEXEC;
|
|
|
|
if (task_spec_ssb_disable(task))
|
|
return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
|
|
|
|
return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
|
|
}
|
|
|
|
int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
|
|
{
|
|
switch (which) {
|
|
case PR_SPEC_STORE_BYPASS:
|
|
return ssbd_prctl_get(task);
|
|
default:
|
|
return -ENODEV;
|
|
}
|
|
}
|